
M
Two-Phase Desktop CPU Core Supply Controllers
with Controlled VID Change
______________________________________________________________________________________
11
Pin Description
PIN
1
2
3
4
5
6
NAME
VID0
VID1
TIME
VID2
VID3
VID4
FUNCTION
Voltage Identification Input Bit 0. See Table 1. Internal 100k
pullup resistor to V
DD
.
Voltage Identification Input Bit 1. See Table 1. Internal 100k
pullup resistor to V
DD
.
Connect to an external resistor (47k
to 470k
) for VID change slew-rate control.
Voltage Identification Input Bit 2. See Table 1. Internal 100k
pullup resistor to V
DD
.
Voltage Identification Input Bit 3. See Table 1. Internal 100k
pullup resistor to V
DD
.
Voltage Identification Input Bit 4. See Table 1. Internal 100k
pullup resistor to V
DD
.
Voltage Positioning. Connect a resistor between VPOS and REF to set the output voltage-positioning
droop, or connect directly to REF for no output voltage positioning. Connect a 47pF capacitor from
VPOS to GND.
IC Analog Power-Supply Input. Connect a 5V supply to V
DD
.
Current-Limit Threshold per Phase. Connect ILIM to V
DD
to set a default current limit of 120mV, or
connect to a voltage-divider from REF to GND to adjust the current limit. See the
Setting the Current
Limit
section.
Ground
Remote Ground Sense. Connect GNDS to the output ground at the load. For VRM applications, also
connect a 100
resistor from GNDS to PGND locally.
Reference Output. Connect a 0.1μF capacitor from REF to GND.
Enable Input. Leave unconnected or drive high for normal operation. Drive low for shutdown.
Remote Feedback Sense. Connect FB to the output at the load. For VRM applications, also connect
a 100
resistor from FB to the output locally.
Power-Good Output. Open-drain output is high impedance when the output is in regulation and
pulled low when the output deviates more than 12.5% from the voltage set by the VID code. PWRGD
is also low in shutdown or during any fault condition. To use as a logic output, connect a pullup
resistor from PWRGD to the logic supply.
7
VPOS
8
V
DD
9
ILIM
10
GND
11
GNDS
12
13
REF
EN
14
FB
15
PWRGD
16
BST2
High-Side MOSFET Gate-Driver Bootstrap Input. Connect 0.22μF or higher value bypass capacitor
from BST2 to LX2. Keep trace length as short as possible. Connect a Schottky diode between BST2
and VLG. See the
Selecting a BST Capacitor
section.
High-Side MOSFET Gate-Drive Output. Connect to the high-side MOSFET gate. DH2 is pulled low in
shutdown.
Inductor Connection. Connect to the switched side of the inductor.
Negative Current-Sense Input. Connect to a current-sense resistor in series with the low-side
MOSFET, or connect to LX2 to use the low-side MOSFET
’
s on-resistance for current sensing.
Low-Side MOSFET Gate-Driver Output. Connect to the low-side MOSFET gate. DL2 is pulled low in
shutdown.
Power Ground. Connect to power ground at the point where the current-sense resistors or low-side
MOSFET sources connect. PGND is used as the positive current-sense connection.
17
DH2
18
LX2
19
CS2
20
DL2
21
PGND