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參數(shù)資料
| 型號： | MAX192ACAP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SERIAL 20-SSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 單電源 |
| 電源電壓： | ±5V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
MAX192
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for single-ended
inputs, IN- is connected to AGND, and the converter
samples the “+” input. If the converter is set up for differ-
ential inputs, IN- connects to the “-” input, and the differ-
ence of
IN+ - IN- is sampled. At the end of the conver-
sion, the positive input connects back to IN+, and
CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acquisi-
tion time lengthens and more time must be allowed
between conversions. Acquisition time is calculated by:
tAZ = 9 (RS + RIN) 16pF
where RIN = 5k, RS = the source impedance of the
input signal, and tAZ is never less than 1.5s. Note that
source impedances below 5kW do not significantly affect
the AC performance of the ADC. Higher source imped-
ances can be used if an input capacitor is connected to
the analog inputs, as shown in Figure 5. Note that the
input capacitor forms an RC filter with the input source
impedance, limiting the ADC’s signal bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
See the data sheets for the MAX291–MAX297 filters.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV, or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
The MAX192 can be configured for differential (unipolar
or bipolar) or single-ended (unipolar only) inputs, as
selected by bits 2 and 3 of the control byte (Table 3).
In the single-ended mode, set the UNI/BIP bit to unipolar.
In this mode, analog inputs are internally referenced to
AGND, with a full-scale input range from 0V to VREF.
In differential mode, both unipolar and bipolar settings
can be used. Choosing unipolar mode sets the differen-
tial input range at 0V to VREF. The output code is invalid
(code zero) when a negative differential input voltage is
applied. Bipolar mode sets the differential input range to
±VREF / 2. Note that in this differential mode, the com-
mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.
Quick Look
To evaluate the analog performance of the MAX192
quickly, use Figure 5’s circuit. The MAX192 requires a
control byte to be written to DIN before each
conversion. Tying DIN to +5V feeds in control bytes of
Low-Power, 8-Channel,
Serial 10-Bit ADC
8
_______________________________________________________________________________________
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
0
+
–
1
0
+
–
0
1
+
–
1
0
1
+
–
0
1
0
+
–
1
0
+
–
0
1
+
–
1
+
–
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