參數(shù)資料
型號: MAX191BEWG+
廠商: Maxim Integrated Products
文件頁數(shù): 23/24頁
文件大小: 0K
描述: IC ADC 12BIT 100KSPS W/REF24SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
位數(shù): 12
采樣率(每秒): 100k
數(shù)據(jù)接口: MICROWIRE?,并聯(lián),QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 941mW
電壓電源: 雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
_______________Detailed Description
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (Ps), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1F capacitor from AIN- to AGND.
Analog Input—Track/Hold
The T/H enters its tracking mode when the ADC is des-
elected (CS pin is held high and BUSY pin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
MAX191
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
8
_______________________________________________________________________________________
DN
3k
CL
DGND
+5V
3k
DN
CL
DGND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Access Time
DN
3k
10pF
DGND
+5V
3k
DN
10pF
DGND
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Bus-Relinquish Time
1
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PD
AIN+
AIN-
VREF
REFADJ
AGND
BIP
BUSY
DO/DB
D1/D9
DGND
VSS
2
VDD
CLK/SCLK
PAR
HBEN
CS
RD
D7/DOUT
D6/SCLKOUT
D5/SSTRB
D4
D3/D11
D2/D10
OPEN
OUTPUT
STATUS
4.7
F
0.1
F
0.1
F
0V TO -5V
+5V
SERIAL/PARALLEL
INTERFACE MODE
P CONTROL
INPUTS
MAX191
C1
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
P DATA BUS
Figure 3. Operational Diagram
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