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參數(shù)資料
| 型號(hào)： | MAX188DEWP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SERIAL 20-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
Data Framing
The falling edge of CS does not start a conversion on the
MAX186/MAX188. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after VCC is applied.
OR
The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto the DOUT pin.
If a falling edge on CS forces a start bit before bit 5
(B5) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX186/MAX188 can run is 15 clocks per
conversion. Figure 11a shows the serial-interface timing
necessary to perform a conversion every 15 SCLK
cycles in external clock mode. If CS is low and SCLK is
continuous, guarantee a start bit by first clocking in 16
zeros.
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX186/MAX188. Figure 11b shows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX186/MAX188 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies have
been stabilized, the internal reset time is 100s and no
conversions should be performed during this phase.
SSTRB is high on power-up and, if CS is low, the first
logical 1 on DIN will be interpreted as a start bit. Until a
conversion takes place, DOUT will shift out zeros.
Reference-Buffer Compensation
In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen-
sation affects both power-up time and maximum conver-
sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.
To select external compensation, open SHDN. See the
Typical Operating Circuit, which uses a 4.7F capacitor at
VREF. A value of 4.7F or greater ensures stability and
allows operation of the converter at the full clock speed of
2MHz. External compensation increases power-up time (see
the
Choosing Power-Down Mode section, and Table 5).
Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal com-
pensation allows for shortest power-up times, but is only
available using an external clock and reduces the maxi-
mum clock rate to 400kHz.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
14
Maxim Integrated
MAX186/MAX188
PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB
SCLK
tCSS
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
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