CLOAD = 100pF 20 150 SCLK Fall to Output Data Valid t
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鍨嬭櫉锛� MAX188CEPP+
寤犲晢锛� Maxim Integrated Products
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鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC ADC 12BIT SERIAL 20-DIP
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
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灏佽/澶栨锛� 20-DIP锛�0.300"锛�7.62mm锛�
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CLOAD = 100pF
20
150
SCLK Fall to Output Data Valid
tDO
MAX18_ _C/E
Note 1: Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX186 鈥� internal reference, offset nulled; MAX188 鈥� external reference (VREF = +4.096V), offset nulled.
Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at VSUPPLY +5% and VSUPPLY -5% only.
Note 9: The common-mode range for the analog inputs is from VSS to VDD.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Maxim Integrated
5
MAX186/MAX188
PARAMETER
SYMBOL
CONDITIONS
UNITS
Positive Supply Rejection
(Note 8)
PSR
卤0.06
卤0.5
mV
Negative Supply Rejection
(Note 8)
PSR
VSS = -5V 卤5%; external reference, 4.096V;
full-scale input
卤0.01
卤0.5
mV
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 卤5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186鈥�
4.7F capacitor at VREF pin; MAX188鈥攅xternal reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise
noted.)
TIMING CHARACTERISTICS
(VDD = 5V 卤5%; VSS =0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
UNITS
SCLK Pulse Width Low
tCL
200
ns
SCLK Fall to SSTRB
tSSTRB
CLOAD = 100pF
200
ns
tSDV
External clock mode only, CLOAD = 100pF
200
ns
tSTR
External clock mode only, CLOAD = 100pF
200
ns
tSCK
Internal clock mode only
0
ns
Acquisition Time
tAZ
1.5
s
DIN to SCLK Setup
tDS
100
ns
DIN to SCLK Hold
tDH
0
ns
CS Fall to Output Enable
tDV
CLOAD = 100pF
100
ns
CS Rise to Output Disable
tTR
CLOAD = 100pF
100
ns
CS to SCLK Rise Setup
tCSS
100
ns
CS to SCLK Rise Hold
tCSH
0
ns
SCLK Pulse Width High
tCH
200
ns
SSTRB Rise to SCLK Rise
(Note 6)
CS Fall to SSTRB Output Enable
(Note 6)
VDD = 5V 卤5%; external reference, 4.096V;
full-scale input
MIN
TYP
MAX
MIN
TYP
MAX
CS Rise to SSTRB Output Disable
(Note 6)
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MAX188CEPP+ 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�:Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX188CEWP 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC Integrated Circuits (ICs) RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�:Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
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MAX188CEWP+ 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�:Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
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