CLOAD DGND DOUT
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MAX188BEAP+
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 23/25闋�
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鎻忚堪锛� IC ADC 12BIT SERIAL 20-SSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 66
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鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 133k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
闆诲闆绘簮锛� 闆� ±
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灏佽/澶栨锛� 20-SSOP锛�0.209"锛�5.30mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-SSOP
鍖呰锛� 绠′欢
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Maxim Integrated
7
MAX186/MAX188
+5V
3k
惟
CLOAD
DGND
DOUT
CLOAD
DGND
3k
惟
DOUT
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
+5V
3k
惟
CLOAD
DGND
DOUT
CLOAD
DGND
3k
惟
DOUT
a VOH to High-Z
b VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disabled Time
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.46V
REFERENCE
(MAX186)
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
VSS
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
AGND
REFADJ
VREF
OUT
REF
CLOCK
+4.096V
20k
惟
鈮� 1.65
1
2
3
4
5
6
7
8
10
11
12
13
15
16
17
18
19
MAX186
MAX188
CS
SHDN
A
20
14
9
Figure 3. Block Diagram
________________________________________________Pin Description (continued)
PIN
NAME
FUNCTION
12
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
VDD.
13
AGND
Analog Ground. Also IN- Input for single-ended conversions.
14
DGND
Digital Ground
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when
CS is high.
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when
CS is high (external mode).
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless
CS is low. When CS is high, DOUT
is high impedance.
19
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20
VDD
Positive Supply Voltage, +5V 卤5%
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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MAX188BEAP+T 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX188BEAP-T 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
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