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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MAX186AEAP+T
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 20/25闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC ADC 12BIT SERIAL 20-SSOP
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯欐簴鍖呰锛� 2,000
椤炲瀷锛� 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�锛孉DC
鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 133k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
闆诲闆绘簮锛� 闆� ±
闆绘簮闆诲锛� ±5V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 20-SSOP锛�0.209"锛�5.30mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 20-SSOP
鍖呰锛� 甯跺嵎 (TR)
Low-Power, 8-Channel,
Serial 12-Bit ADCs
4
Maxim Integrated
MAX186/MAX188
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V 卤5%; VSS = 0V or -5V; fCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186鈥�
4.7F capacitor at VREF pin; MAX188鈥攅xternal reference, VREF = 4.096V applied to VREF pin; TA = TMIN to TMAX, unless otherwise
noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Internal compensation mode
0
F
Capacitive Bypass at VREF
External compensation mode
4.7
MAX186
1.678
V/V
MAX188
1.638
MAX186
卤50
A
REFADJ Input Current
MAX188
卤5
VINH
2.4
V
VINL
0.8
V
DIN, SCLK, CS Input Hysteresis
VHYST
0.15
V
DIN, SCLK, CS Input Leakage
IIN
VIN = 0V or VDD
卤1
A
CIN
(Note 6)
15
pF
SHDN Input High Voltage
VINH
VDD - 0.5
V
SHDN Input Low Voltage
VINL
0.5
V
SHDN Input Current, High
IINH
VSHDN = VDD
4.0
A
SHDN Input Current, Low
IINL
VSHDN = 0V
-4.0
A
SHDN Input Mid Voltage
VIM
V
SHDN Voltage, Open
VFLT
VSHDN = open
2.75
V
VSHDN = open
-100
100
nA
ISINK = 5mA
0.4
Output Voltage Low
VOL
ISINK = 16mA
0.3
V
Output Voltage High
VOH
ISOURCE = 1mA
4
V
Three-State Leakage Current
IL
VCS = 5V
卤10
A
Three-State Output Capacitance
COUT
VCS = 5V (Note 6)
15
pF
Positive Supply Voltage
VDD
5 卤5%
V
DIN, SCLK, CS Input Capacitance
SHDN Max Allowed Leakage,
Mid Input
Negative Supply Voltage
VSS
0 or
-5 卤5%
V
Operating mode
1.5
2.5
Fast power-down
30
70
Positive Supply Current
IDD
Full power-down
210
Operating mode and fast power-down
50
Negative Supply Current
ISS
Full power-down
10
A
mA
A
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input High Voltage
1.5
VDD -1.5
DIGITAL INPUTS (DIN, SCLK, C
CS
S, S
SH
HD
DN
N)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
UNITS
EXTERNAL REFERENCE AT REFADJ
Reference-Buffer Gain
鐩搁棞PDF璩囨枡
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鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉)
鍙冩暩(sh霉)鎻忚堪
MAX186AEPP 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞夋彌鍣� - ADC Integrated Circuits (ICs) RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲愭:Sigma-Delta 杞夋彌閫熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX186AEPP+ 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞夋彌鍣� - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲愭:Sigma-Delta 杞夋彌閫熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX186AEWP 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞夋彌鍣� - ADC Integrated Circuits (ICs) RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲愭:Sigma-Delta 杞夋彌閫熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX186AEWP+ 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞夋彌鍣� - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲愭:Sigma-Delta 杞夋彌閫熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32
MAX186AEWP+T 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞夋彌鍣� - ADC 12-Bit 8Ch 133ksps 5.25V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲愭:Sigma-Delta 杞夋彌閫熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32