參數(shù)資料
型號: MAX1865UEEP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: xDSL/Cable Modem Triple/Quintuple Output Power Supplies
中文描述: 0.5 A SWITCHING CONTROLLER, 120 kHz SWITCHING FREQ-MAX, PDSO20
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-20
文件頁數(shù): 20/25頁
文件大?。?/td> 384K
代理商: MAX1865UEEP
M
xDSL/Cable Modem Triple/Quintuple Output
Power Supplies
20
______________________________________________________________________________________
Transistor Selection
The pass transistors must meet specifications for cur-
rent gain (h
FE
), input capacitance, collector-emitter sat-
uration voltage, and power dissipation. The transistor
s
current gain limits the guaranteed maximum output cur-
rent to:
where I
DRV
is the minimum base-drive current, and R
BE
(220
) is the pullup resistor connected between the
transistor
s base and emitter. Furthermore, the transis-
tor
s current gain increases the linear regulator
s DC
loop gain (see
Stability Requirements
), so excessive
gain will destabilize the output. Therefore, transistors
with current gain over 100 at the maximum output cur-
rent, such as Darlington transistors, are not recom-
mended. The transistor
s input capacitance and input
resistance also create a second pole, which could be
low enough to destabilize the output when heavily
loaded.
The transistor
s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator will support.
Alternatively, the package
s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power dissipation capability of
the transistor
s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pated equals the maximum load current times the maxi-
mum input-to-output voltage differential:
(
(
)
Stability Requirements
The MAX1864/MAX1865 linear regulators use an inter-
nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, pass
transistor
s specifications, the base-emitter resistor,
and the output capacitor determine the loop stability. If
the output capacitor and pass transistor are not proper-
ly selected, the linear regulator will be unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor
s base cur-
rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain
(A
V (LDO)
) is approximately:
where V
T
is 26mV, and I
BIAS
is the current through the
base-to-emitter resistor (R
BE
). This bias resistor is typical-
ly 220
, providing approximately 3.2mA of bias current.
The output capacitor creates the dominant pole.
However, the pass transistor
s input capacitance creates
a second pole in the system. Additionally, the output
capacitor
s ESR generates a zero, which may be used to
cancel the second pole if necessary. Therefore, to
achieve stable operation, use the following equations to
verify that the linear regulator is properly compensated:
1) First, determine the dominant pole set by the linear
regulator
s output capacitor and the load resistor:
2) Next, determine the second pole set by the base-to-
emitter capacitance (including the transistor
s input
capacitance), the transistor
s input resistance, and
the base-to-emitter pullup resistor:
3) A third pole is set by the linear regulator
s feedback
resistance and the capacitance between FB_ and
GND, including 20pF stray capacitance:
4) If the second and third poles occur well after unity-
gain crossover, the linear regulator will remain stable:
However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with
POLE(FB)
by changing
circuit components such that:
>
2
POLE CBE
POLE CLDO
(
V LDO
(
A
(
)
)
)
=
POLE FB
FB
C
R
(
R
(
)
||
)
1
2
1
2
π
=
(
)
=
+
POLE CBE
BE
C
π
BE
IN NPN
R
V h
BELOAD
BE BE T FE
2
C
R
R
(
)
(
)
||
1
2
π
=
=
=
POLE CLDO
(
LDO LOAD
C
π
LOAD MAX
I
C
2
π
LDO LDO
V LDO
(
POLE CLDO
(
Unity GainCrossover
A
)
(
)
)
)
1
2
A
V
I
I
V
V LDO
(
T
BIAS FE
LOAD
REF
)
.
+
5 5
1
P
I
V
V
I
V
LOAD MAX
LDOIN
OUT
LOAD MAX
CE
=
)
=
(
)
-
I
I
V
R
h
LOAD MAX
DRV
BE
BE
FE MIN
(
(
)
)
=
-
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