V
TRIP
is the input voltage where the low-battery detec-
tor output goes high impedance.
For single-cell applications, LBI may be connected to
the battery. When V
BATT
<1.0V>, the LBI threshold
increases to 0.925V (see
Typical Operating Char-
acteristics
).
Connect a pullup resistor of 100k
or greater from LBO
to OUT for a logic output. LBO is an open-drain output
and can be pulled as high as 6V regardless of the volt-
age at OUT. When LBI is below the threshold, the LBO
output is high impedance. If the low-battery comparator
is not used, ground LBI and LBO.
Applications Information
Inductor Selection
An inductor value of 22μH performs well in most appli-
cations. The MAX1795/MAX1796/MAX1797 will also
work with inductors in the 10μH to 47μH range. Smaller
inductance values typically offer a smaller physical size
for a given series resistance, allowing the smallest
overall circuit dimensions, but have lower output cur-
rent capability. Circuits using larger inductance values
exhibit higher output current capability, but are physi-
cally larger for the same series resistance and current
rating.
The inductor
’
s incremental saturation current rating
should be greater than the peak switch-current limit,
which is 0.25A for the MAX1795, 0.5A for the MAX1796,
and 1A for the MAX1797. However, it is generally
acceptable to bias the inductor into saturation by as
much as 20% although this will slightly reduce efficien-
cy. Table 1 lists some suggested components for typi-
cal applications.
The inductor
’
s DC resistance significantly affects effi-
ciency. Calculate the maximum output current
(I
OUT(MAX)
) as follows, using inductor ripple current
(I
RIP
) and duty cycle (D):
and
where: I
RIP
= Inductor ripple current (A)
V
OUT
= Output voltage (V)
I
LIM
= Device current limit (0.25A, 0.5A, or 1A)
R
PFET
= On-resistance of P-channel MOSFET
(
) (typ 0.27
)
L
ESR
= ESR of Inductor (
) (typ 0.095
)
V
BATT
= Input voltage (V)
L = Inductor value in μH
t
OFF
= LX switch
’
s off-time (μs) (typ 1μs)
D = Duty cycle
R
NFET
= On-resistance of N-channel MOSFET
(
) (typ 0.17
)
I
OUT(MAX)
= Maximum output current (A)
Capacitor Selection
Table 1 lists suggested tantalum or polymer capacitor
values for typical applications. The ESR of both input
bypass and output filter capacitors affects efficiency
and output ripple. Output voltage ripple is the product
of the peak inductor current and the output capacitor
ESR. High-frequency output noise can be reduced by
connecting a 0.1μF ceramic capacitor in parallel with
the output filter capacitor. (See Table 2 for a list of sug-
gested component suppliers.)
PC Board Layout and Grounding
Careful printed circuit layout is important for minimizing
ground bounce and noise. Keep the IC
’
s GND pin and
the ground leads of the input and output filter capaci-
tors less than 0.2in (5mm) apart. In addition, keep all
connections to the FB and LX pins as short as possible.
In particular, when using external feedback resistors,
locate them as close to FB as possible. To maximize
output power and efficiency and minimize output ripple
voltage, use a ground plane and solder the IC
’
s GND
pin directly to the ground plane.
I
I
I
D
OUT MAX
(
LIM
RIP
2
)
(
)
=
1
I
=
D =
RIP
V
I
R
L
V
L
t
R
L
V
I
I
R
L
V
V
I
I
R
R
OUT
LIM
PFET
ESR
BATT
OFF
PFET
ESR
OUT
LIM
RIP
2
PFET
ESR
BATT
OUT
LIM
RIP
2
PFET
NFET
+
(
+
+
2
)
(
)
+
(
+
)
+
(
+
L
ESR
)
M
Low Supply Current, Step-Up DC-DC Converters
with True-Shutdown
______________________________________________________________________________________
11