
M
Small, Dual, High-Efficiency
Buck Controller for Notebooks
18
______________________________________________________________________________________
A dual N-channel and a dual P-channel MOSFET
(Figure 8)
Two single N-channels and a dual P-channel
(Figure 9)
Two single N-channels and two single P-channels
(Figure 10)
There are trade-offs to each approach. Complementary
devices have appropriately scaled N- and P-channel
R
DS(ON)
and matched turn-on/turn-off characteristics.
However, there are relatively few manufacturers of
these specialized devices. Selection may be limited.
Dual N- and P-channel MOSFETs are more widely
available. As such, more efficient designs that benefit
from the large low-side MOSFETs can be realized. This
approach is most useful when the output power
requirements for both regulators are about the same.
This limitation can be sidestepped by using a dual P-
channel and two single N-channels. Using four single
MOSFETs gives the greatest design flexibility but will
require the most board area.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation (P
D
) due to resistance occurs at the
minimum battery voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation limits often limits how small the MOS-
FET can be. The optimum occurs when the switching
(AC) losses equal the conduction (R
DS(ON)
) losses.
High-side switching losses don
’
t usually become an
issue until the input is greater than approximately 15V.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV
2
F switching-loss equation. If the high-side MOSFET
you
’
ve chosen for adequate R
DS(ON)
at low battery volt-
ages becomes extraordinarily hot when subjected to
V+
(MAX)
, reconsider your MOSFET choice.
Calculating the power dissipation in Q1 due to switch-
ing losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turn-
off times. These factors include the internal gate resis-
tance, gate charge, threshold voltage, source
inductance, and PC board layout characteristics. The
following switching-loss calculation provides only a
very rough estimate and is no substitute for breadboard
evaluation, preferably including a verification using a
thermocouple mounted on Q1:
where C
RSS
is the reverse transfer capacitance of Q1,
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
For the low-side MOSFET (Q2) the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
LOAD (MAX)
but are not quite high enough to exceed the
current limit and cause the fault latch to trip. To protect
against this possibility, the circuit must be overdesigned
to tolerate:
I
LOAD
= I
LIMIT (MAX)
+ 1/2
LIR
I
LOAD (MAX)
P (Q2)
V
V+
I
Rs
OUT
(MAX)
OAD2
L
=
×
×
1
P (Q1 switching)
C
V+
I
I
RSS
(MAX)
LOAD
GATE
2
=
×
××
P (Q1 resistance)
V
V+
I
R
OUT
(MIN)
OAD2
L
DS(ON)
=
×
×
P-CHANNEL
LX1
DH1
V+
DL1
D
G
D
S
D
G
D
S
N-CHANNEL
1
P-CHANNEL
LX2
DH2
V+
DL2
D
G
D
S
D
G
D
S
N-CHANNEL
1
Figure 7. Dual Complementary MOSFET Design