參數(shù)資料
型號: MAX148ACAP+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/23頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SERIAL 20-SSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 10
采樣率(每秒): 133k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 640mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
12
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
The T/H acquires the input signal as the last three bits of
the control byte are clocked into DIN. Bits PD1 and PD0
of the control byte program the clock mode. Figures 7–10
show the timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive- approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (Figure 6). SSTRB
and DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic-low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time, or
droop on the sample-and-hold capacitors may degrade
conversion results. Use internal clock mode if the serial-
clock frequency is less than 100kHz, or if serial-clock
interruptions could cause the conversion interval to
exceed 120Fs.
tDO
SCLK
DIN
DOUT
CS
tCSS
tDS
tDH
tDV
tTR
tCSH
tCL
tCH
tCSH
PD0 CLOCKED IN
SCLK
tSSTRB
SSRTB
CS
tSDV
tSTR
tSSTRB
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