參數(shù)資料
型號: MAX147EVC32-DIP
廠商: Maxim Integrated Products
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: EVAL KIT FOR MAX147
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 133k
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF/2
在以下條件下的電源(標準): 2.7mW @ 133kSPS
工作溫度: 0°C ~ 70°C
已用 IC / 零件: MAX147
已供物品: 2 板,樣品,CD
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
16
______________________________________________________________________________________
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. The100kHz minimum clock rate is limited by
droop on the sample-and-hold and is independent of
the compensation used.
Float SHDN to select external compensation. The
Typical Operating Circuit uses a 4.7F capacitor at
VREF. A 4.7F value ensures reference-buffer stability
and allows converter operation at the 2MHz full clock
speed. External compensation increases power-up
time (see the Choosing Power-Down Mode section and
Table 4).
Pull SHDN high to select internal compensation.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down mode or fast power-down mode via bits 1
and 0 of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current to 2A
(typ). Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30A. Power-up time can be
shortened to 5s in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7F compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 12a and 12b show
the various power-down sequences in both external and
internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active and conversion
results may be clocked out after the MAX146/MAX147
enter a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX146/MAX147. Following
the start bit, the data input word or control byte also
determines clock mode and power-down states. For
example, if the DIN word contains PD1 = 1, then the
chip remains powered up. If PD0 = PD1 = 0, a
power-down resumes after one conversion.
Table 4. Typical Power-Up Delay Times
133
2
Full
Disabled
133
2
Fast
Disabled
133
See Figure 14c
Full
4.7
External
Enabled
133
See Figure 14c
Fast
4.7
External
Enabled
26
300
Full
Internal
Enabled
26
5
Fast
Internal
Enabled
MAXIMUM
SAMPLING RATE
(ksps)
POWER-UP
DELAY
(s)
POWER-DOWN
MODE
VREF
CAPACITOR
(F)
REFERENCE-
BUFFER
COMPENSATION
MODE
REFERENCE
BUFFER
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