- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9856 > MAX146BCPP+ (Maxim Integrated Products)IC ADC LP 12-BIT 133KSPS 20-DIP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX146BCPP+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/24闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC LP 12-BIT 133KSPS 20-DIP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 18 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 133k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 889mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 20-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 20-PDIP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 8 鍊嬪柈绔�锛屽柈妤�锛�8 鍊嬪柈绔�锛岄洐妤�锛�4 鍊嬪樊鍒�锛屽柈妤碉紱4 鍊嬪樊鍒�锛岄洐妤� |
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PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB
SCLK
DOUT
tCSS
tDO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
14
______________________________________________________________________________________
processor鈥檚 convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5s (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX146/MAX147 and three-states DOUT, but it
does not adversely affect an internal clock mode
conversion already in progress. When internal clock
mode is selected, SSTRB does not go into a high-
impedance state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX146/MAX147 at clock rates exceeding 2.0MHz
if the minimum acquisition time (tACQ) is kept above
1.5s.
SSTRB
CS
SCLK
DIN
DOUT
14
8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
B11
MSB
B10
B9
B2
B1
B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5
s MAX
(SHDN = FLOAT)
2
3
5
6
7
9
10
11
19
21
22
23
tCONV
ACQUISITION
(fSCLK = 2MHz)
IDLE
A/D STATE
1.5
s
Figure 9. Internal Clock Mode Timing
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| D38999/20WF11SE | CONN RCPT 11POS WALL MNT W/SCKT |
| VI-JNR-MX-F3 | CONVERTER MOD DC/DC 7.5V 75W |
| MS27473E18A35SB | CONN PLUG 66POS STRAIGHT W/SCKT |
| VI-JNR-MX-F2 | CONVERTER MOD DC/DC 7.5V 75W |
| VI-JNR-MX-F1 | CONVERTER MOD DC/DC 7.5V 75W |
鐩搁棞浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX146BCPP+ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 3.6V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX146BEAP | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 3.6V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX146BEAP/GH9 | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX146BEAP/GH9-T | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX146BEAP+ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 8Ch 133ksps 3.6V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
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