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參數(shù)資料
| 型號(hào)： | MAX145AEPA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | LJT 37C 37#22M PIN PLUG |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AB, DIP-8 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 240K |
| 代理商： | MAX145AEPA |
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_______________Detailed Desc ription
The MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (μPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
Analog Inputs: S ingle-Ended (MAX 144)
and Pseudo-Differential (MAX 145)
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the
CS
/SHDN pin. Conversions can be performed on
the same channel by toggling
CS
/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1μF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. The
acquisition interval spans from when
CS
/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when
CS
/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on C
HOLD
as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
M
+2.7V, Low-Power, 2-Channel, 108ksps,
S erial 12-Bit ADCs in 8-Pin μMAX
_______________________________________________________________________________________
7
6k
C
L
DOUT
a)
HIGH-Z TOV
0H
, V
0L
TOV
0H
, AND V
OH
TOHIGH-Z
6k
C
L
GND
DOUT
GND
V
DD
b)
HIGH-Z TOV
0L
, V
0H
TOV
0L
, AND V
OL
TOHIGH-Z
Figure 1. Load Circuits for Enable and Disable Time
MAX144
MAX145
12-BIT
SAR
ADC
SCLK
( ) ARE FOR MAX145
IN
OUT
ANALOG
INPUT
MUX
(2 CHANNEL)
CH0
(CH+)
CH1
(CH-)
REF
T/H
CONTROL
LOGIC
SCLK
CS/SHDN
INTERNAL
CLOCK
OUTPUT
REGISTER
DOUT
Figure 2. Simplified Functional Diagram
CH0
(CH+)
CH1
(CH-)
( ) ARE FOR MAX145
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
R
IN
9k
ZERO
REF
GND
TRACK
HOLD
COMPARATOR
TOSAR
T/H
C
HOLD
16pF
INPUT
MUX
12-BIT CAPACITIVE DAC
C
SWITCH
CONTROL LOGIC
MAX144
MAX145
Figure 3. Analog Input Channel Structure
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX144AEUA | LJT 21C 21#16 SKT PLUG |
| MAX145AEUA | Circular Connector; No. of Contacts:21; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:23; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:23-21 RoHS Compliant: No |
| MAX144BEPA | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| MAX145BEPA | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| MAX144BEUA | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX145AEPA+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX145AEUA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX145AEUA+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX145AEUA+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX145AEUA-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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