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參數(shù)資料
| 型號： | MAX144BCPA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001AB, DIP-8 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 240K |
| 代理商： | MAX144BCPA |
M
External Referenc e
An external reference is required for both the MAX144
and the MAX145. At REF, the DC input resistance is a
minimum of 18k
. During a conversion, a reference
must be able to deliver 250μA of DC load current and
have an output impedance of 10
or less. Use a 0.1μF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to V
DD
+
50mV, although noise levels will decrease effective res-
olution at lower reference voltages.
Automatic Power-Down Mode
Whenever the MAX144/MAX145 are not selected
(
CS
/SHDN = V
DD
), the parts enter their shutdown
mode. In shutdown all internal circuitry turns off, reduc-
ing supply current to typically less than 0.2μA. With an
external reference stable to within 1LSB, the wake-up
time is 2.5μs. If the external reference is not stable with-
in 1LSB, the wake-up time must be increased to allow
the reference to stabilize.
__________Applic ations Information
S ignal-to-Noise Ratio (S NR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR
(MAX)
= (6.02
·
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
S ignal-to-Noise Plus Distortion (S INAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to RMS equivalent of all other ADC out-
put signals:
Effec tive Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists only of quantization noise. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:
ENOB = (SINAD - 1.76) / 6.02
T otal Harmonic Distortion (T HD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
S purious-Free Dynamic Range (S FDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connec tion to S tandard Interfac es
The MAX144/MAX145 interface is fully compatible with
SPI, QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX144/MAX145. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS
/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (t
WAKE
) speci-
fied before activating SCLK.
3) Activate SCLK for a minimum of 16 clock cycles.
The serial data stream of three leading ones, the
channel identification, and the MSB of the digitized
input signal begin at the first falling clock edge.
DOUT transitions on SCLK’s falling edge and is
available in MSB-first format. Observe the SCLK to
THD = 20 log
V
+ V
+ V
+ V
V
22
32
42
52
1
SINAD(dB) = 20 log
Signal
(Noise + Distortion)
RMS
RMS
+2.7V, Low-Power, 2-Channel, 108ksps,
S erial 12-Bit ADCs in 8-Pin μMAX
10
______________________________________________________________________________________
Table 1. Serial Output Data Stream for Internal and External Clock Mode
SCLK CYCLE
DOUT (Internal Clock)
DOUT (External Clock)
1
2
1
1
3
1
1
4
5
6
7
8
9
10
D6
D6
11
D5
D5
12
D4
D4
13
D3
D3
14
D2
D2
15
D1
D1
16
D0
D0
EOC
1
CHID D11
CHID D11
D10
D10
D9
D9
D8
D8
D7
D7
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX144BCPA+ | 功能描述:模數(shù)轉換器 - ADC 12-Bit 2Ch 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX144BCUA | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX144BCUA+ | 功能描述:模數(shù)轉換器 - ADC 12-Bit 2Ch 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX144BCUA+T | 功能描述:模數(shù)轉換器 - ADC 12-Bit 2Ch 108ksps 5.25V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX144BCUA-T | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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