參數(shù)資料
型號(hào): MAX1415EUE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 10/36頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT DELTA SIGMA 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 500
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 755mW
電壓電源: 單電源
工作溫度: -45°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極;2 個(gè)差分,雙極
MAX1415/MAX1416
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
18
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
SCLK
Serial Clock Input. Apply an external serial clock to transfer data to and from the device at data rates
up to 5MHz.
2
CLKIN
Clock Input. Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with
a CMOS-compatible clock source. Connect CLKIN to GND when using the internal oscillator.
3
CLKOUT
Clock Output. Connect a crystal/resonator between CLKIN and CLKOUT. When enabled, CLKOUT
provides a CMOS-compatible, inverted clock output. CLKOUT can drive one CMOS load. Set CLKDIS
= 0 in the clock register to enable CLKOUT. Set CLKDIS = 1 in the clock register to disable CLKOUT.
4
CS
Active-Low Chip-Select Input.
CS selects the active device in systems with more than one device on
the serial bus. Drive
CS low to clock data in on DIN and to clock data out on DOUT. When CS is high,
DOUT is high impedance. Connect
CS to GND for 3-wire operation.
5
RESET
Active-Low Reset Input. Drive
RESET low to reset the MAX1415/MAX1416 to power-on reset status.
6
AIN2+
Channel 2 Positive Analog Input
7
AIN1+
Channel 1 Positive Analog Input
8
AIN1-
Channel 1 Negative Analog Input
9
REF+
Positive Reference Input
10
REF-
Negative Reference Input
11
AIN2-
Channel 2 Negative Analog Input
12
DRDY
Active-Low Data Ready Output.
DRDY goes low when a new conversion result is available in the data
register. When a read operation of a full output word completes,
DRDY returns high.
13
DOUT
Serial Data Output. DOUT outputs serial data from the data register. DOUT changes on the falling
edge of SCLK and is valid on the rising edge of SCLK. When
CS is high, DOUT is high impedance.
14
DIN
Serial Data Input. Data on DIN is clocked in on the rising edge of SCLK when
CS is low.
15
VDD
Power Input. Connect VDD to a 2.7V to 3.6V power supply for the MAX1415, and connect VDD to a
4.75V to 5.25V power supply for the MAX1416.
16
GND
Ground
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