參數(shù)資料
型號(hào): MAX1401EAI+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 15/36頁(yè)
文件大小: 0K
描述: IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 750µW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 3 個(gè)差分,單極;3 個(gè)差分,雙極;5 個(gè)偽差分,單極;5 個(gè)偽差分,雙極
MAX1401
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
22
______________________________________________________________________________________
Table 11. Channel ID Tag Codes
Switching Network
A switching network provides selection between three
fully differential input channels or five pseudo-differen-
tial channels, using AIN6 as a shared common. The
switching network provides two additional fully differen-
tial input channels intended for system calibration,
which may be used as extra fully differential signal
channels. Table 12 shows the channel configurations
available for both operating modes.
Scanning (SCAN Mode)
To sample and convert the available input channels
sequentially, set the SCAN control bit in the global
setup register. The sequence is determined by DIFF
(fully differential or pseudo-differential) and by the
mode control bits M1 and M0 (Tables 8, 9, and 10).
With SCAN set, the part automatically sequences
through each available channel, transmitting a single
conversion result before proceeding to the next chan-
nel. The MAX1401 automatically allows sufficient time
for each conversion to fully settle, to ensure optimum
resolution before asserting the data-ready signal and
moving to the next available channel. The scan rate,
therefore, depends on the clock bit (CLK), the filter
control bits (FS1, FS0), and the modulator frequency
selection bits (MF1, MF0).
Burn-Out Currents
The input circuitry also provides two “burn-out” cur-
rents. These small currents may be used to test the
integrity of the selected transducer. They can be selec-
tively enabled or disabled by the BOUT bit in the global
setup register.
CHANNEL
CID2
1
AIN1–AIN2
AIN5–AIN6
1
Calibration
1
0
1
AIN3–AIN4
1
0
AIN1–AIN6
AIN3–AIN6
0
AIN4–AIN6
1
0
1
0
AIN2–AIN6
1
0
CID0
0
CID1
0
Table 12. Input Channel Configuration in Fully Differential and Pseudo-Differential
Mode (SCAN = 0)
X = Don’t care
* This combination is available only in pseudo-differential mode when using the internal scanning logic.
** These combinations are only available in the calibration modes.
0
M0
0
DIFF
0
AIN2
0
AIN4
0
AIN3
AIN1
0
1
0
1
AIN3
0
1
X
CALOFF+**
0
AIN5
AIN1
0
X
1
X
CALOFF+**
M1
0
X
HIGH INPUT
CALGAIN+**
AIN5*
1
0
X
CALGAIN+**
1
0
A1
0
1
0
1
X
MODE
Pseudo-
Differential
Fully
Differential
0
A0
1
0
1
0
1
0
X
AIN6
AIN4
CALOFF-**
AIN6
AIN2
CALOFF-**
LOW INPUT
CALGAIN-**
AIN6*
CALGAIN-**
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