參數(shù)資料
型號: MAX1395ETB+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/18頁
文件大小: 0K
描述: IC ADC 10BIT 357KSPS 10-TDFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
位數(shù): 10
采樣率(每秒): 357k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 830µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤
供應商設備封裝: 10-TDFN-EP(3x3)
包裝: 標準包裝
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
產品目錄頁面: 1396 (CN2011-ZH PDF)
其它名稱: MAX1395ETB+TDKR
MAX1392/MAX1395
Detailed Description
The MAX1392/MAX1395 use an input track and hold
(T/H) circuit along with a SAR to convert an analog input
signal to a serial 10-bit digital output data stream. The
serial interface provides easy interfacing to microproces-
sors and DSPs. Figure 3 shows the simplified functional
diagram for the MAX1392 (1 channel, true differential)
and the MAX1395 (2 channels, single ended).
True-Differential Analog Input T/H
The equivalent input circuit of Figure 4 shows the
MAX1392/MAX1395 input architecture, which is com-
posed of a T/H, a comparator, and a switched-capacitor
DAC. The T/H enters its tracking mode on the falling
edge of CS (while OE is held low). The positive input
capacitor is connected to AIN+ (MAX1392), or to AIN1 or
AIN2 (MAX1395). The negative input capacitor is con-
nected to AIN- (MAX1392) or GND (MAX1395). The T/H
enters its hold mode on the 3rd falling edge of SCLK
8
_______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
PIN
MAX1392
MAX1395
NAME
FUNCTION
11
VDD
Positive Supply Voltage. Connect VDD to a 1.5V to 3.6V power supply. Bypass VDD to GND
with a 0.1F capacitor as close to the device as possible.
2
AIN-
Negative Analog Input
2
AIN2
Analog Input Channel 2
3
AIN+
Positive Analog Input
3
AIN1
Analog Input Channel 1
4
GND
Ground
5
REF
External Reference Voltage Input. VREF = 0.6V to (VDD + 0.05V). Bypass REF to GND with a
0.1F capacitor as close to the device as possible.
6
UNI/BIP
Input-Mode Select. Drive UNI/BIP high to select unipolar input mode. Pull UNI/BIP low to
select bipolar input mode. In unipolar mode, the output data is in straight binary format. In
bipolar mode, the output data is in two’s-complement format.
—6
CH1/CH2
Channel-Select Input. Pull CH1/CH2 low to select channel 1. Drive CH1/CH2 high to select
channel 2.
77
OE
Active-Low Output Enable. Pull OE low to enable DOUT. Drive OE high to disable DOUT.
Connect to CS to interface with SPI, QSPI, and MICROWIRE devices or set low to interface
with DSP devices.
88
CS
Active-Low Chip-Select Input. A falling edge on CS initiates power-up and acquisition.
9
DOUT
Serial-Data Output. DOUT changes state on the falling edge of SCLK. DOUT is high
impedance when OE is high.
10
SCLK
Serial-Clock Input. SCLK drives the conversion process and clocks data out. Acquisition ends
on the 3rd falling edge after the CS falling edge. The LSB is clocked out on the SCLK 13th
falling edge and the device enters AutoShutdown mode (see Figures 8, 9, and 10).
——
EP
Exposed Pad. Not internally connected. Connect the exposed pad to GND or leave
unconnected.
Pin Description
DOUT
VDD
REF
10-BIT SAR
ADC
CS
SCLK
OE
GND
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC AND
TIMING
*INDICATES THE MAX1395
AIN+ (AIN1)*
AIN- (AIN2)*
INPUT
MUX
AND T/H
UNI/BIP
(CH1/CH2)*
MAX1392
MAX1395
Figure 3. Simplified Functional Diagram
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