參數(shù)資料
型號(hào): MAX13482EETE+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/19頁
文件大?。?/td> 0K
描述: IC TXRX USB ESD PROT 16-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: USB 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: USB 2.0
電源電壓: 4 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(3x3)
包裝: 帶卷 (TR)
MAX13481E/MAX13482E/MAX13483E
±15kV ESD-Protected USB Transceivers with
External/Internal Pullup Resistors
10
______________________________________________________________________________________
VTRM
An internal linear regulator generates the VTRM voltage
(+3.3V, typ). VTRM derives power from VBUS (see the
Power-Supply Configurations section). VTRM powers
the internal portions of the USB circuitry and provides
the pullup voltage for the MAX13481E/MAX13482E.
Bypass VTRM to GND with a 1F ceramic capacitor as
close to the device as possible. Do not use VTRM to pro-
vide power to any other external circuitry.
D+ and D-
D+ and D- serve as bidirectional bus connections and
are ESD-protected to ±15kV (Human Body Model). For
OE = low, D+ and D- serve as transmitter outputs. For
OE = high, D+ and D- serve as receiver inputs.
BD (MAX13482E/MAX13483E)
The push-pull bus detect (BD) output monitors VBUS
and asserts high if VBUS is greater than VTH_H. BD
asserts low if VBUS is less than VTH_L, and the
MAX13482E/MAX13483E enter sharing mode (Table 2).
VBUS
For most applications, VBUS connects to the VBUS ter-
minal on the USB connector (see the Power-Supply
Configurations section). VBUS can also connect to an
external supply. Drive VBUS low to enable sharing
mode. Bypass VBUS to GND with a 1F ceramic capac-
itor as close to the device as possible.
External Components
External Capacitors
The MAX13481E/MAX13482E/MAX13483E require
three external capacitors for proper operation. Bypass
VL to GND with a 0.1F ceramic capacitor. Bypass
VBUS to GND with a 1F ceramic capacitor. Bypass
VTRM to GND with a 1F (min) ceramic capacitor.
Install all capacitors as close to the device as possible.
External Resistor
Proper USB operation requires two external resistors,
each 27
Ω ±1%. Install one resistor in series between D+
of the MAX13481E/MAX13482E/MAX13483E and D+ on
the USB connector. Install the other resistor in series
between D- of the MAX13481E/MAX13482E/MAX13483E
and D- on the USB connector (see the Typical Operating
Circuits). The MAX13483E requires an external 1.5k
Ω
pullup resistor between VTRM and D+ for full-speed
operation. The MAX13481E requires an external 1.5k
Ω
pullup resistor between VPU and D+ for full-speed oper-
ation. The MAX13482E does not require an external
pullup resistor but VPUR must be connected to D+ for
full-speed operation.
Data Transfer
Transmitting Data to the USB
To transmit data to the USB, drive
OE low. The
MAX13481E/MAX13482E/MAX13483E transmit data to
the USB differentially on D+ and D-. VP and VM serve
as input signals to the differential driver and are also
used to assert a single-ended zero (SE0) driver (see
Table 3).
Receiving Data from the USB
To receive data from the USB, drive
OE high and SUS
low. Differential data received by D+ and D- appears at
RCV. Single-ended receivers on D+ and D- drive VP
and VM, respectively.
RCV
RCV monitors D+ and D- when receiving data. RCV is a
logic 1 for D+ high and D- low. RCV is a logic 0 for D+
low and D- high. RCV retains its last valid state when
D+ and D- are both low (single-ended zero, or SE0).
ESD Protection
D+ and D- possess extra protection against static elec-
tricity to protect the devices up to
±15kV. The ESD
structures withstand high ESD in all operating modes:
normal operation, suspend mode, and powered down.
D+ and D- provide protection to the following limits:
±15kV using the Human Body Model
±8kV using the Contact Discharge method specified
in IEC 61000-4-2
To protect VBUS from ±15kV ESD, a 1F or greater
capacitor must be connected from VBUS to GND.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 6 shows the Human Body Model and Figure 7
shows the current waveform generated when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which then discharges into the test device through
a 1.5k
Ω resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. It does not specifi-
cally refer to integrated circuits. The major difference
between tests done using the Human Body Model and
IEC 61000-4-2 is a higher peak current in IEC 61000-4-
2, due to lower series resistance. Hence, the ESD with-
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