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參數(shù)資料
| 型號： | MAX1346BETX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 25/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/FIFO 36WQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 225k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
31
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
MSB1
tDOV
LSB1
MSB2
(CONVERSION BYTE)
CS
DOUT
SCLK
DIN
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (
CNVST is not required).
and averaging registers to correctly update the FIFO.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
If averaging is turned on, multiple
CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switch-
es the analog-input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of
CNVST follow-
ing the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once
EOC has been pulled low.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a com-
mand byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1340/MAX1342/MAX1346/
MAX1348 then power up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete,
EOC is pulled low and the results are
available in the FIFO. If a temperature measurement is
requested, the temperature result precedes all other
FIFO results.
EOC stays low until CS is pulled low again.
Wait until all conversions are complete before reading
the FIFO. SPI communications to the DAC and GPIO
registers are permitted during conversion. However,
coupled noise may result in degraded ADC SNR.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1347BETX | 制造商:Maxim Integrated Products 功能描述:12-BIT, MULTICHANNEL ADCS/DACS WITH FIFO, TEM - Rail/Tube |
| MAX1347BETX+ | 制造商:Maxim Integrated Products 功能描述:12-BIT MULTICHANNEL ADCS/DACS WITH - Rail/Tube |
| MAX1347BETX+T | 制造商:Maxim Integrated Products 功能描述:12-BIT MULTICHANNEL ADCS/DACS WITH - Tape and Reel |
| MAX1347BETX-T | 制造商:Maxim Integrated Products 功能描述:12-BIT, MULTICHANNEL ADCS/DACS WITH FIFO, TEM - Tape and Reel |
| MAX13481EETE | 功能描述:USB 接口集成電路 RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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