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參數(shù)資料
| 型號： | MAX13342EETD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX USB FS 3WIRE 14-TDFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 14-TDFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VBUS = +4V to +5.5V, VL = +2.3V to +3.6V, ENUM = VL, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VBUS =
+5V, VL = +2.5V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMITTER ( CL = 50pF)
Rise Time
tFR
10% to 90% of |VOHD-VOLD| with an external
31.6
series resistor (MAX13342E),
Figures 3, 8
420
ns
Fall Time
tFF
10% to 90% of |VOHD-VOLD| with an external
31.6
series resistor (MAX13342E),
Figures 3, 8
420
ns
Rise-and-Fall Time Matching
(Note 1)
tLR/tLF
Figures 3, 8
90
110
%
Output Signal Crossover (Note 2)
VCRS_L,
VCRS_F
Figure 4
1.3
2
V
tPLH_DRV
Low-to-high transition,
Figures 4, 8
VL > 2.3V
20
Driver
Propagation Delay
tPHL_DRV
High-to-low transition,
Figures 4, 8
VL > 2.3V
20
ns
tPZH_DRV
Off-to-high transition,
Figures 5, 8
VL > 2.3V
18
Driver-Enabled Delay Time
tPZL_DRV
Off-to-low transition,
Figures 5, 8
VL > 2.3V
18
ns
tPHZ_DRV
High-to-off transition,
Figure 5, 9
VL > 2.3V
18
Driver Disable Delay
tPLZ_DRV
Low-to-off transition,
Figures 5, 9
VL > 2.3V
18
ns
RECEIVER (CL = 15pF)
tPLH_RCV
Low-to-high transition,
Figures 6,10
VL > 2.3V
20
Differential Receiver
Propagation Delay
tPHL_RCV
High-to-low transition,
Figures 6,10
VL > 2.3V
20
ns
tPLH_SE
Low-to-high transition,
Figures 6,10
18
Single-Ended Receiver
Propagation Delay
tPHL_SE
High-to-low transition,
Figures 6,10
18
ns
tPHZ_SE
High-to-off transition,
Figure 7
VL > 2.3V
20
Single-Ended Receiver Disable
Delay
tPLZ_SE
Low-to-off transition,
Figure 7
VL > 2.3V
20
ns
tPZH_SE
Off-to-high transition,
Figure 7
VL > 2.3V
22
Single-Ended Receiver Enable
Delay
tPZL_SE
Off-to-low transition,
Figure 7
VL > 2.3V
22
ns
Note 1: Parameters are 100% production tested at +25°C, unless otherwise noted. Limits over temperature are guaranteed by design.
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