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參數(shù)資料
| 型號： | MAX1306ECM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 2CH 1.8MSPS 48LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.8M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.82W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
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MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX1314
Reading a Conversion Result
Reading During a Conversion
Figures 7 and 8 show the interface signals to initiate a
read operation during a conversion cycle. These figures
show two channels selected for conversion. If more
channels are selected, the results are available succes-
sively at every EOC falling edge. CS can be low at all
times, low during the RD cycles, or the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC to go low. In internal clock mode, EOC
goes low within 900ns. In external clock mode, EOC
goes low on the rising edge of the 13th CLK cycle. To
read the conversion result, drive CS and RD low to
latch data to the parallel digital output bus. Bring RD
high to release the digital bus. In internal clock mode,
the next EOC falling edge occurs within 225ns. In exter-
nal clock mode, the next EOC falling edge occurs in
three CLK cycles. When the last result is available
EOLC goes low.
Reading After Conversion
Figure 9 shows the interface signals for a read operation
after a conversion with all eight channels enabled. At
the falling of EOLC, driving CS and RD low places the
first conversion result onto the parallel bus. Successive
low pulses of RD place the successive conversion
results onto the bus. When the last conversion results in
the sequence are read, additional read pulses wrap the
pointer back to the first converted result.
CONVST
CLK
CH3
TRACK
HOLD
D0–D11
SAMPLE
INSTANT
tACQ
tCNTC
tCTR
tRDH
tRTC
tACC
tRDL
tREQ
TRACK
CH7
EOC
RD
1
2
3
12
13
14
15
16
17
18
19
1
tCLK
tEOCD
tCONV
tNEXT
tEOC
tEOCD
tCLKH
tEOLCD
tCVEOLCD
tQUIET
≥ 50ns
tCLKL
EOLC
CS*
*CS CAN BE LOW AT ALL TIMES, LOW DURING THE RD CYCLES, OR THE SAME AS RD.
Figure 8. Read During Conversion—Channel 3 and Channel 7 Selected, External Clock
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________
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