參數(shù)資料
型號(hào): MAX13037ATX+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/22頁(yè)
文件大小: 0K
描述: IC AUTO CONTACT MONITOR 36-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
應(yīng)用: 自動(dòng)
接口: SPI
電源電壓: 6 V ~ 26 V
封裝/外殼: 36-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-TQFN 裸露焊盤(6x6)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
MAX13037/MAX13038
Automotive Contact Monitor and
Level Shifters with LDO Regulator
10
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
19
SD
Shutdown Input. Drive
SD low to place the MAX13037/MAX13038 into shutdown mode and disable
the linear regulator. Drive
SD high for normal operation. SD is compatible with voltages up to VBAT.
20
REGON
Linear Regulator Enable Input (Active Low). Connect
REGON to INT to enable a wake-up when a
switch status change is detected. Drive
REGON using an open-drain logic output to control the
regulator directly.
REGON is internally pulled up to an internal bias voltage of approximately +4.8V.
21
REGOFF
Linear Regulator Disable Input (Active Low).
REGOFF is used in conjunction with REGON when the
internal regulator is enabled by an interrupt (see the Low-Dropout Linear Regulator (VLO) section).
22
CS
SPI Chip-Select Input. Drive
CS low to enable the clocking of data into and out of the
MAX13037/MAX13038. SPI data is latched into the MAX13037/MAX13038 on the rising edge of
CS.
23
SDO
SPI Serial-Data Output. SPI data is output on SDO on the rising edges of CLK while
CS is held low.
SDO is three-state when
CS is high.
24
SDI
SPI Serial-Data Input. SPI data is latched into the internal shift register on the falling edges of CLK
while
CS is held low. SDI has an internal 100k
Ω pulldown resistor.
25
CLK
SPI Serial-Clock Input
26
RST
Reset Output.
RST is an open-drain output that asserts low when VLO is below the threshold
determined by the THRESH input.
RST also asserts low when the watchdog times out.
27
DO1
Data Output Channel 1. DO1 is the level-shifted output of IN1 when WEND = 0.
28
DO0
Data Output Channel 0. DO0 is the level-shifted output of IN0 when WEND = 0.
29
THRESH
Reset Threshold Level Input. Connect THRESH to a resistor divider between VLO and GND to set the
reset reference level.
30
WDI
Watchdog Timer Input. The watchdog timer is reset at every transition on the WDI input.
32
BATREF
Battery Reference Input. Switch thresholds are set to 50% of the voltage applied to BATREF. Connect
BATREF to the system’s battery supply voltage.
33
VLO
Linear Regulator Output. VLO is the output of an internal linear regulator and is the reference voltage
for all digital I/O. Bypass VLO with a 2.2F or greater ceramic capacitor. Alternatively, a 10F
electrolytic capacitor can be used in parallel with a 0.1F ceramic capacitor.
35, 36
BAT
Battery Supply Input. Connect BAT to a positive +6V to +26V battery supply voltage. Bypass BAT to
ground with a 0.1F ceramic capacitor and a 10F electrolytic capacitor placed as close as possible
to BAT.
EP
Exposed Paddle. Connect EP to GND.
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