參數(shù)資料
型號: MAX1302BEUG+
廠商: Maxim Integrated Products
文件頁數(shù): 16/31頁
文件大?。?/td> 0K
描述: IC ADC 16BIT SRL 115KSPS 24TSSOP
標準包裝: 62
位數(shù): 16
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.11W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
User supplies one byte of SCLK, then drives CS
high to relieve processor load while the ADC
converts
After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
External Clock Mode (Mode 0)
The MAX1302’s fastest maximum throughput rate is
achieved operating in external clock mode. SCLK con-
trols both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is
at the falling edge of the 14th SCLK (Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1302 will
always be used in the external clock mode.
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
______________________________________________________________________________________
23
CS
SCLK
DIN
DOUT
18
START
SEL2
SEL1
SEL0
R2
R1
R0
DIF/SGL
tCL
tCP
tCH
tDV
tCSS
tDS
tDH
tCSH
tCSPW
tTR
HIGH
IMPEDANCE
18
START
M2
M1
M0
1
0
ANALOG INPUT CONFIGURATION BYTE
MODE CONTROL BYTE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
CS
SCLK
DOUT
tCSS
HIGH IMPEDANCE
SSTRB
tSSCS
MSB
tDO
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
Figure 16. DOUT and SSTRB Timing
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME
DESCRIPTION
7
START
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
6M2
5M1
4M0
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
3
1
Bit 3 must be a logic 1 for the mode-control byte.
2
0
Bit 2 must be a logic 0 for the mode-control byte.
1
0
Bit 1 must be a logic 0 for the mode-control byte.
0
Bit 0 must be a logic 0 for the mode-control byte.
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