8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADC" />
參數資料
型號: MAX1300BEUG+
廠商: Maxim Integrated Products
文件頁數: 4/31頁
文件大小: 0K
描述: IC ADC 16BIT SPI/SRL 24TSSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 62
位數: 16
采樣率(每秒): 115k
數據接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數目: 1
功率耗散(最大): 976mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 24-TSSOP
包裝: 管件
輸入數目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,雙極
MAX1300/MAX1301
8- and 4-Channel, ±3 x VREF Multirange Inputs,
Serial 16-Bit ADCs
12
______________________________________________________________________________________
Pin Description
PIN
MAX1300 MAX1301
NAME
FUNCTION
1
2
AVDD1
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass
AVDD1 to AGND1 with a 0.1F capacitor.
2
3
CH0
Analog Input Channel 0
3
4
CH1
Analog Input Channel 1
4
5
CH2
Analog Input Channel 2
5
6
CH3
Analog Input Channel 3
6
CH4
Analog Input Channel 4
7
CH5
Analog Input Channel 5
8
CH6
Analog Input Channel 6
9
CH7
Analog Input Channel 7
10
7
CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the
rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.
When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.
11
8
DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.
12
9
SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that
data is ready to be read from the device. When operating in external clock mode, SSTRB is
always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
13
10
SCLK
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.
14
11
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.
15
12
DGNDO
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
16
13
DGND
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
17
14
DVDDO
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage.
Bypass DVDDO to DGNDO with a 0.1F capacitor.
18
15
DVDD
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.
Bypass DVDD to DGND with a 0.1F capacitor.
19
16
REFCAP
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD.
For internal reference operation, bypass REFCAP with a 0.01F capacitor to AGND1
(VREFCAP
≈ 4.096V).
20
17
REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
bypassing REF with a 1F capacitor to AGND1 sets VREF = 4.096V ±1%.
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MAX1300BEUG+ 功能描述:模數轉換器 - ADC 16-Bit 8Ch 115ksps 4.136V Precision ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1300BEUG+T 功能描述:模數轉換器 - ADC 16-Bit 8Ch 115ksps 4.136V Precision ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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