參數(shù)資料
型號: MAX13003EEUE+
廠商: Maxim Integrated Products
文件頁數(shù): 10/25頁
文件大?。?/td> 0K
描述: IC LEVEL TRANS 6CH 16-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 96
邏輯功能: 變換器,雙向
位數(shù): 6
輸入類型: CMOS
輸出類型: CMOS
數(shù)據(jù)速率: 20Mbps
通道數(shù): 1
輸出/通道數(shù)目: 6
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 15ns
電源電壓: 1.5 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
MAX13000E–MAX13005E
IEC 61000-4-2 Standard ESD Protection
The IEC 61000-4-2 standard (Figure 12) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330
Ω resistor. The
MAX13000E–MAX13005E’s I/O on the VCC side are
rated for IEC 61000-4-2 standard, (8kV Contact
Discharge and ±10kV Air-Gap Discharge).
The IEC 61000-4-2 model discharges higher peak cur-
rent and more energy than the HBM due to the lower
series resistance and larger capacitor.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass VL and VCC to ground with a 0.1F
capacitor. To ensure full ±15kV ESD protection, bypass
VCC to ground with a 1F capacitor. Place all capaci-
tors as close to the power-supply inputs as possible.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to Maxim application note:
Wafer-Level Chip-Scale Package.
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Ultra-Low-Voltage Level Translators
18
______________________________________________________________________________________
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
RC 1M
Ω
RD 1500
Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
CS
100pF
Figure 10. Human Body ESD Test Model
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50
Ω TO 100Ω
RD
330
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 12. IEC 61000-4-2 Contact Discharge Test Model
100%
90%
36.8%
tRL
tDL
TIME
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
10%
0
AMPERES
IP
Ir
Figure 11. Human Body Current Waveform
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