參數(shù)資料
型號(hào): MAX1297BEEG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24
封裝: 0.150 INCH, QSOP-28
文件頁(yè)數(shù): 9/20頁(yè)
文件大?。?/td> 228K
代理商: MAX1297BEEG
M
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
_______________________________________________________________________________________
9
BIT
PD1, PD0
0
D7, D6
PD1
and
PD0
select the various clock and power-down modes.
Full Power-Down Mode. Clock mode is unaffected.
D5
ACQMOD
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
NAME
FUNCTIONAL DESCRIPTION
0
1
0
Standby Power-Down Mode. Clock mode is unaffected.
0
1
1
Normal Operation Mode. External clock mode selected.
1
Normal Operation Mode. Internal clock mode selected.
D4
SGL
/DIF
SGL
/DIF
= 0: Pseudo-Differential Analog Input Mode
SGL
/DIF
= 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2, 4).
D3
UNI
/BIP
UNI/
BIP
= 0: Bipolar Mode
UNI/
BIP
= 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
REF
can be converted; in bipolar mode, the
signal can range from -V
REF
/2 to +V
REF
/2.
D2, D1, D0
A2, A1, A0
Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted
(Tables 2, 3).
Table 1. Control-Byte Functional Description
the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5LSB
(±0.1LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1μF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on C
HOLD
as a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
Figure 3a. MAX1295 Simplified Input Structure
Figure 3b. MAX1297 Simplified Input Structure
CH0
CH1
CH2
CH3
CH4
CH5
COM
C
SWITCH
TRACK
T/H
SWITCH
R
IN
800
C
HOLD
HOLD
12-BIT CAPACITIVE DAC
V
REF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
CH0
CH1
COM
C
SWITCH
TRACK
T/H
SWITCH
R
IN
800
C
HOLD
HOLD
12-BIT CAPACITIVE DAC
V
REF
ZERO
COMPARATOR
+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
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