M
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
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7
Pin Description
D0
10
10
INT
11
11
RD
12
12
WR
13
13
CLK
14
14
D4
6
6
D3
7
7
D2
8
8
D1
9
9
D5
5
5
D6
4
4
1
D7
3
3
D8
2
2
D9
1
Three-State Digital I/O Line (D0)
INT
goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If
CS
is low, a falling edge on
RD
will enable the read oper-
ation on the data bus.
Active-Low Write Select. When
CS
is low in the internal acquisition mode, a rising
edge on
WR
latches in configuration data and starts an acquisition plus a conver-
sion cycle. When
CS
is low in external acquisition mode, the first rising edge on
WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either V
DD
or GND.
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D7)
Three-State Digital Output (D8)
Three-State Digital Output (D9)
GND
19
23
REFADJ
20
24
CH2
—
19
CH1
16
20
CH0
17
21
COM
18
22
CH3
—
18
CH4
—
17
CH5
—
16
CS
15
15
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01μF capacitor. When using an external reference, connect REFADJ to V
DD
to
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When
CS
is high, digital outputs (
INT
, D11–D0) are high
impedance.
PIN
MAX1297
MAX1295
NAME
FUNCTION
