• 參數(shù)資料
    型號(hào): MAX128BCNG+
    廠商: Maxim Integrated Products
    文件頁(yè)數(shù): 12/16頁(yè)
    文件大?。?/td> 0K
    描述: IC DAS 12BIT 2-WIRE 24-DIP
    產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
    Obsolescence Mitigation Program
    標(biāo)準(zhǔn)包裝: 15
    類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
    分辨率(位): 12 b
    采樣率(每秒): 8k
    數(shù)據(jù)接口: I²C,串行
    電壓電源: 單電源
    電源電壓: 4.75 V ~ 5.25 V
    工作溫度: 0°C ~ 70°C
    安裝類型: 通孔
    封裝/外殼: 24-DIP(0.300",7.62mm)
    供應(yīng)商設(shè)備封裝: 24-PDIP
    包裝: 管件
    MAX127/MAX128
    Multirange, +5V, 12-Bit DAS with
    2-Wire Serial Interface
    _______________________________________________________________________________________
    5
    ELECTRICAL CHARACTERISTICS (continued)
    (VDD = +5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 400kHz;
    TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.)
    Input Hysteresis
    VHYS
    0.05 x VDD
    V
    Input Low Threshold Voltage
    VIL
    0.3 x VDD
    V
    Input High Threshold Voltage
    VIH
    0.7 x VDD
    V
    PARAMETER
    SYMBOL
    MIN
    TYP
    MAX
    UNITS
    CONDITIONS
    TIMING CHARACTERISTICS
    (VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; TA = TMIN to TMAX;
    unless otherwise noted. Typical values are at TA = +25°C.)
    Input Capacitance
    CIN
    15
    pF
    (Note 4)
    Input Leakage Current
    IIN
    ±0.1
    ±10
    A
    VIN = 0 or VDD
    Three-State Output Capacitance
    COUT
    15
    pF
    (Note 4)
    Output Low Voltage
    VOL
    0.4
    V
    ISINK = 3mA
    2-WIRE FAST MODE
    Hold Time (Repeated)
    START Condition
    tHD,STA
    0.6
    s
    Bus Free Time Between a
    STOP and START Condition
    tBUF
    1.3
    s
    SCL Clock Frequency
    fSCL
    400
    kHz
    PARAMETERS
    SYMBOL
    MIN
    TYP
    MAX
    UNITS
    CONDITIONS
    Set-Up Time for a Repeated
    START Condition
    tSU,STA
    0.6
    s
    High Period of the SCL Clock
    tHIGH
    0.6
    s
    Low Period of the SCL Clock
    tLOW
    1.3
    s
    Rise Time for Both SDA and SCL
    Signals (Receiving)
    tR
    20 +
    300
    0.1 x Cb
    ns
    Cb = Total capacitance of one bus line in pF
    Data Setup Time
    tSU,DAT
    100
    ns
    Data Hold Time
    tHD,DAT
    0
    0.9
    s
    DIGITAL INPUTS (SDA, SCL)
    DIGITAL OUTPUTS (SDA)
    ISINK = 6mA
    0.6
    Fall Time for Both SDA and SCL
    Signals (Receiving)
    tF
    Cb = Total capacitance of one bus line in pF
    20 +
    300
    0.1 x Cb
    ns
    Fall Time for Both SDA and SCL
    Signals (Transmitting)
    tF
    Cb = Total capacitance of one bus line in pF
    20 +
    250
    0.1 x Cb
    ns
    Set-Up Time for STOP Condition
    tSU,STO
    0.6
    s
    Capacitive Load for Each
    Bus Line
    Cb
    400
    pF
    Pulse Width of Spike Suppressed
    tSP
    0
    50
    ns
    2-WIRE FAST MODE
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