參數(shù)資料
型號: MAX1289ETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/15頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 150KSPS 8-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 150k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 2 個(gè)單端,單極;2 個(gè)單端,雙極;1 個(gè)差分,單極;1 個(gè)差分,雙極
產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
其它名稱: MAX1289ETA+TDKR
MAX1286–MAX1289
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (VDD) may
degrade the performance of the ADC’s fast comparator.
Bypass VDD to the star ground with a 0.1F capacitor,
located as close as possible to the MAX1286–MAX1289s’
power-supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5
) if
the power supply is extremely noisy.
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
12
______________________________________________________________________________________
CNVST
SCLK
DOUT
CS
SCK
MISO
VDD
SS
QSPI
MAX1286–
MAX1289
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
CONTROL BIT
MAX1286–MAX1289
SETTINGS
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
SMP
Bit 7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data
output time.
CKE
Bit 6
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial
clock.
D/A
Bit 5
X
Data Address Bit
P
Bit 4
X
Stop Bit
S
Bit 3
X
Start Bit
R/W
Bit 2
X
Read/Write Bit Information
UA
Bit 1
X
Update Address
BF
Bit 0
X
Buffer Full Status Bit
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
CNVST
1ST BYTE READ
SCLK
DOUT
2ND BYTE READ
SAMPLING INSTANT
4
18
12
B11
MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
HIGH-Z
16
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