參數(shù)資料
型號: MAX1286ETA+T
廠商: Maxim Integrated Products
文件頁數(shù): 13/15頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 150KSPS 8-TDFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
位數(shù): 12
采樣率(每秒): 150k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應商設(shè)備封裝: 8-TDFN-EP(3x3)
包裝: 標準包裝
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極;1 個差分,單極;1 個差分,雙極
產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
其它名稱: MAX1286ETA+TDKR
MAX1286–MAX1289
150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs
_______________________________________________________________________________________
7
Detailed Description
The MAX1286–MAX1289 ADCs use a successive-
approximation conversion (SAR) technique and an on-
chip track-and-hold (T/H) structure to convert an
analog signal into a 12-bit digital result.
The serial interface provides easy interfacing to micro-
processors (Ps). Figure 3 shows the simplified internal
structure for the MAX1286/MAX1287 (2 channels, sin-
gle ended) and the MAX1288/MAX1289 (1 channel,
true differential).
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the
MAX1286–MAX1289s’ input architecture, which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1286/
MAX1287) or AIN+ (MAX1288/MAX1289). The negative
input capacitor is connected to GND (MAX1286/
MAX1287) or AIN- (MAX1288/MAX1289). The T/H enters
its hold mode on the falling edge of CNVST and the dif-
ference between the sampled positive and negative
input voltages is converted. The time required for the
T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input sig-
nal’s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
period of time. The acquisition time, tACQ, is the maxi-
mum time needed for the signal to be acquired, plus the
power-up time. It is calculated by the following equation:
tACQ = 9 x (RS + RIN) x 24pF + tPWR
12-BIT
SAR
ADC
CONTROL
OSCILLATOR
INPUT SHIFT
REGISTER
T/H
REF
CNVST
SCLK
DOUT
AIN2
(AIN-)
AIN1
(AIN+)
MAX1286–MAX1289
( ) ARE FOR MAX1288/MAX1289
Figure 3. Simplified Functional Diagram
NAME
PIN
MAX1286
MAX1287
MAX1288
MAX1289
FUNCTION
1VDD
VDD
Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V
(MAX1286/MAX1288). Bypass with a 0.1F capacitor to GND.
2
AIN1
AIN+
Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)
3
AIN2
AIN-
Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)
4
GND
Ground
5
REF
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1F
capacitor to GND.
6
CNVST
Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).
7
DOUT
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high
impedance once data has been fully clocked out.
8
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
EP
Exposed Pad. Connect the exposed pad to ground or leave unconnected.
Pin Description
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