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參數(shù)資料
| 型號(hào)： | MAX1286EKA-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-178, SOT-23, 8 PIN |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | MAX1286EKA-T |
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M
150ksps, 12-Bit, 2-Channel S ingle-Ended, and
1-Channel True-Differential ADCs in S OT 23
10
______________________________________________________________________________________
Output Data Format
Figures 5a and 5b illustrate the conversion timing for the
MAX1286
–
MAX1289. The 12-bit conversion result is out-
put in MSB-first format. Data on DOUT transitions
on the falling edge of SCLK. All 12 bits must be clocked
out before CNVST transitions again. For the MAX1288/
MAX1289, data is straight binary for unipolar mode and
two
’
s complement for bipolar mode. For the MAX1286/
MAX1287, data is always straight binary.
T ransfer Func tion
Figure 6 shows the unipolar transfer function for the
MAX1286
–
MAX1289. Figure 7 shows the bipolar transfer
function for the MAX1288/MAX1289. Code transitions
occur halfway between successive-integer LSB values.
Applic ations Information
Automatic S hutdown Mode
With CNVST low, the MAX1286
–
MAX1289 default to an
AutoShutdown state (<0.2μA) after power-up and
between conversions. After detecting a rising edge on
CNVST, the part powers up, sets DOUT low, and enters
track mode. After detecting a falling edge on CNVST, the
device enters hold mode and begins the conversion. A
maximum of 3.7μs later, the device completes conver-
sion, enters shutdown, and MSB is available at DOUT.
External Referenc e
An external reference is required for the MAX1286
–
MAX1289. Use a 0.1μF bypass capacitor for best per-
formance. The reference input structure allows a volt-
age range of +1V to V
DD
+ 50mV.
Connection to Standard Interfaces
The MAX1286
–
MAX1289 feature a serial interface that is
fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU
’
s serial
interface as a master, so that the CPU generates the seri-
al clock for the ADCs. Select a clock frequency up to
8MHz.
How to Perform a Conversion
Use a general-purpose I/O line on the CPU to hold
CNVST low between conversions.
Drive CNVST high to acquire AIN1(MAX1286/
MAX1287) or unipolar mode (MAX1288/MAX1289).
To acquire AIN2 (MAX1286/MAX1287) or bipolar
mode (MAX1288/MAX1289), drive CNVST low and
high again.
Hold CNVST high for 1.4μs.
Drive CNVST low and wait approximately 3.7μs for
conversion to complete. After 3.7μs, the MSB is
available at DOUT.
Activate SCLK for a minimum of 12 rising clock
1)
2)
3)
4)
5)
OUTPUT CODE
FULL-SCALE
TRANSITION
11
. . .
111
11
. . .
110
11
. . .
101
00
. . .
011
00
. . .
010
00
. . .
001
00
. . .
000
1
2
3
0
FS
FS - 3/2LSB
FS = V
REF
ZS = GND
1LSB = V
REF
INPUT VOLTAGE (LSB)
MAX1286
–
MAX1289
4096
Figure 6. Unipolar Transfer Function
011
. . .
111
011
. . .
110
000
. . .
010
000
. . .
001
000
. . .
000
111
. . .
111
111
. . .
110
111
. . .
101
100
. . .
001
100
. . .
000
- FS
0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1LSB
*V
COM
V
REF
/ 2 *V
IN
= (AIN+) - (AIN-)
FS
= V
REF
2
-FS = -V
REF
2
MAX1288/MAX1289
1LSB = V
REF
4096
Figure 7. Bipolar Transfer Function
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