參數(shù)資料
型號(hào): MAX1285
廠商: Maxim Integrated Products, Inc.
英文描述: 400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
中文描述: 400ksps/300ksps、單電源、低功耗、串行12位ADC,內(nèi)置電壓基準(zhǔn)
文件頁數(shù): 5/15頁
文件大小: 210K
代理商: MAX1285
M
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
_______________________________________________________________________________________
5
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
CS
Pulse Width High
t
CSO
t
CS1
t
DOH
t
DOV
t
DOD
t
DOE
t
CSW
35
35
10
ns
ns
ns
ns
ns
ns
ns
SCLK Rise to
CS
Rise Hold
t
CSH
0
ns
CS
Fall to SCLK Rise Setup
t
CSS
35
ns
SCLK Pulse Width Low
t
CL
62
ns
80
65
65
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
SCLK Pulse Width High
t
CH
62
ns
PARAMETER
SYMBOL
t
CP
MIN
156
TYP
MAX
UNITS
ns
CONDITIONS
SCLK Period
TIMING CHARACTERISTICS
MAX1284 (Figures 1, 2, 8, 9)
(V
DD
= +4.5V to +5.5V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
TIMING CHARACTERISTICS
MAX1285 (Figures 1, 2, 8, 9)
(V
DD
= +2.7V to +3.6V, T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
PARAMETER
SYMBOL
Note 1:
Tested at V
DD
= V
DD(MIN)
.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
Internal reference, offset, and reference errors nulled.
Note 4:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:
External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6:
Electrical characteristics are guaranteed from V
DD(MIN)
to V
DD(MAX)
. For operations beyond this range, see
Typical
Operating Characteristics
.
Note 7:
MAX1284 tested with 20pF on D
OUT
and f
SCLK
= 6.4MHz, 0 to 5V. MAX1285 tested with same loads, f
SCLK
= 4.8MHz,
0 to 3V. D
OUT
= full scale.
10
100
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to DOUT Valid
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
CS
Pulse Width High
t
CSO
t
CS1
t
DOH
t
DOV
t
DOD
t
DOE
t
CSW
45
45
13
ns
ns
ns
ns
ns
ns
ns
SCLK Rise to
CS
Rise Hold
t
CSH
0
ns
CS
Fall to SCLK Rise Setup
t
CSS
45
ns
SCLK Pulse Width Low
t
CL
83
ns
100
85
85
13
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
100
SCLK Period
SCLK Pulse Width High
t
CP
t
CH
208
83
ns
MIN
TYP
MAX
UNITS
ns
CONDITIONS
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