參數資料
型號: MAX1281BCUP+T
廠商: Maxim Integrated Products
文件頁數: 7/24頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 300KSPS 20-TSSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數: 12
采樣率(每秒): 300k
數據接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數目: 1
功率耗散(最大): 559mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數目和類型: 8 個單端,單極;8 個單端,雙極;4 個偽差分,單極;4 個偽差分,雙極
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
15
Serial Clock
The external serial clock not only shifts data in and out,
but also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the next
12 SCLK falling edges (Figure 6). SSTRB and DOUT go
into a high-impedance state when CS goes high; after
the next CS rising edge, SSTRB outputs a logic low.
Figure 7 shows the detailed serial-interface timing.
The conversion must complete in 120s or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does
not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge after the eighth bit of
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after VDD1 and VDD2
are applied.
OR
The first high bit clocked into DIN after bit 6 of a con-
version in progress is clocked onto the DOUT pin.
Once a start bit has been recognized, the current con-
version may only be terminated by pulling SHDN low.
The fastest the MAX1280/MAX1281 can run with CS
held low between conversions is 16 clocks per conver-
sion. Figure 8 shows the serial-interface timing neces-
sary to perform a conversion every 16 SCLK cycles. If
CS is tied low and SCLK is continuous, guarantee a
start bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1280/MAX1281 in normal operating mode, ready to
convert with SSTRB = low. The MAX1280/MAX1281
require 10s to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logic 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.
Power Modes
You can save power by placing the converter in one of
the two low-current operating modes or in full power-
down between conversions. Select the power mode
through bit 1 and bit 0 of the DIN control byte (Tables 1
and 4), or force the converter into hardware shutdown
by driving SHDN to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
SCLK
DIN
DOUT
SSTRB
tCSS
tCH
tCSO
tCL
tDH
tDS
tDOE
tSTE
tCSW
tCP
tCSH
tCS1
tSTD
tDOD
tDOV
tDOH
tSTV
tSTH
CS
Figure 7. Detailed Serial-Interface Timing
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MAX1281BEUP+T 功能描述:模數轉換器 - ADC 12-Bit 8Ch 300ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1281BEUP-T 功能描述:模數轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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