參數(shù)資料
型號: MAX1280EVKIT
廠商: Maxim Integrated Products
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: EVAL KIT FOR MAX1280
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 400k
數(shù)據(jù)接口: 串行
輸入范圍: ±VREF/2
在以下條件下的電源(標(biāo)準(zhǔn)): 13.75mW @ 400kSPS
工作溫度: 0°C ~ 70°C
已用 IC / 零件: MAX1280
已供物品: 板,CD
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
10
______________________________________________________________________________________
Pin Description
Positive Supply Voltage
VDD2
19
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1.
REFADJ
12
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
SSTRB
15
Serial Data Input. Data is clocked in at SCLK’s rising edge.
DIN
16
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
CS
17
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
SCLK
18
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a +2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
VDD1.
REF
11
Analog and Digital Ground
GND
13
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
DOUT
14
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2A
(typ).
SHDN
10
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
COM
9
PIN
Sampling Analog Inputs
CH0–CH7
1–8
FUNCTION
NAME
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
VDD2
6k
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
6k
DOUT
a) VOH to High-Z
b) VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
Positive Supply Voltage
VDD1
20
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