參數(shù)資料
型號: MAX127BENG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
中文描述: SPECIALTY ANALOG CIRCUIT, PDIP24
封裝: PLASTIC, DIP-24
文件頁數(shù): 12/16頁
文件大小: 124K
代理商: MAX127BENG
M
Start a Conversion (Write Cycle)
A conversion cycle begins with the master issuing a
START condition followed by seven address bits
(Figure 3) and a write bit (R/
W
= 0). Once the eighth bit
has been received and the address matches, the
MAX127/MAX128 (the slave) issues an acknowledge
by pulling SDA low for one clock cycle (A = 0). The
master then writes the input control byte to the slave
(Figure 8). After this byte of data, the slave issues
another acknowledge, pulling SDA low for one clock
cycle. The master ends the write cycle by issuing a
STOP condition (Figure 6).
When the write bit is set (R/
W
= 0), acquisition starts as
soon as Bit 2 (BIP) of the input control-byte has been
latched and ends when a STOP condition has been
issued. Conversion starts immediately after acquisition.
The MAX127/MAX128’s internal conversion clock fre-
quency is 1.56MHz, resulting in a typical conversion
time of 7.7μs. Figure 9 shows a complete write cycle.
Read a Conversion (Read Cycle)
Once a conversion starts, the master does not need to
wait for the conversion to end before attempting to read
the data from the slave. Data access begins with the
master issuing a START condition followed by a 7-bit
address (Figure 3) and a read bit (R/
W
= 1). Once the
eighth bit has been received and the address matches,
the slave issues an acknowledge by pulling low on SDA
for one clock cycle (A = 0) followed by the first byte of
serial data (D11–D4, MSB first). After the first byte has
been issued by the slave, it releases the bus for the
master to issue an acknowledge (A = 0). After receiv-
ing the acknowledge, the slave issues the second byte
(D3–D0 and four zeros) followed by a NOT acknowl-
edge (
A
= 1) from the master to indicate that the last
data byte has been received. Finally, the master issues
a STOP condition (P), ending the read cycle (Figure 7).
Multirange, +5V, 12-Bit DAS with
2-Wire S erial Interfac e
12
______________________________________________________________________________________
LSB
MSB
SDA
SCL
START SEL2
SEL1 SEL0
RNG
BIP
PD1
PD0
ACK
START: FIRST LOGIC “1” RECEIVED AFTER ACKNOWLEDGE OF A WRITE.
ACK: ACKNOWLEDGE BIT. THE MAX127/MAX128 PULL SDA LOW DURING THE
9TH CLOCK PULSE.
Figure 8. Command Byte
Figure 9. Complete 2-Wire Serial Write Transmission
START
CONDITION
STOP
CONDITION
CONTROL BYTE
SLAVE ADDRESS BYTE
SCL
A/D STATE
SDA
MSB
MSB
LSB
LSB
W
1
2
7
8
9
10
11
15
16
ACQUISITION
17
18
BIP
S
1
0
PD1
PD0
A
A
CONVERSION
MASTER TOSLAVE
SLAVE TO MASTER
NO. OF BITS
S SLAVE ADDRESS W
A
CONTROL-BYTE
A
P
1
7
1 1
8
1 1
START CONDITION
WRITE
ACKNOWLEDGE
ACKNOWLEDGE
STOP CONDITION
MASTER TOSLAVE
SLAVE TO MASTER
NO. OF BITS
S SLAVE ADDRESS R
A DATA-BYTE
A
1
7
1 1
8
1
DATA-BYTE
A P
8
1 1
START CONDITION
READ
NOT ACKNOWLEDGE
ACKNOWLEDGE
STOP CONDITION
Figure 6. Write Cycle
Figure 7. Read Cycle
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