參數(shù)資料
型號: MAX1271BCNG+
廠商: Maxim Integrated Products
文件頁數(shù): 7/20頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 8CH 24-DIP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 15
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 12 b
采樣率(每秒): 110k
數(shù)據(jù)接口: 串行
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應商設備封裝: 24-PDIP
包裝: 管件
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________________________________
15
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Bypass REF with a 4.7F capacitor to AGND and
REFADJ with a 0.01F capacitor to AGND (Figure 13a).
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
To use the REF input directly, disable the internal buffer
by tying REFADJ to VDD (Figure 13b). Using the
REFADJ input eliminates the need to buffer the refer-
ence externally. When a reference is applied at
REFADJ, bypass REFADJ with a 0.01F capacitor to
AGND. Note that when an external reference is applied
at REFADJ, the voltage at REF is given by:
VREF = 1.6384 x VREFADJ (2.4 < VREF < 4.18)
(Figure 13c). At REF and REFADJ, the input impedance
is a minimum of 10k for DC currents. During conver-
sions, an external reference at REF must be able to deliv-
er 400A DC load currents and must have an output
impedance of 10 or less. If the reference has higher
output impedance or is noisy, bypass REF with a 4.7F
capacitor to AGND as close to the chip as possible.
With an external reference voltage of less than 4.096V
at REF or less than 2.5V at REFADJ, the increase in the
ratio of RMS noise to the LSB value (full-scale / 4096)
results in performance degradation (loss of effective
bits).
CS
SCLK
DIN
DOUT
A/D STATE
1
8
9
24
22
14
16
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
D11 D10 D9
D7
D8
D6 D5
D4
D2
D3
D1 D0
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
START
SEL0
SEL1
SEL2
CONTROL BYTE
RESULT
CONTROL BYTE 1
CONTROL BYTE 2
13 SCLK
SSTRB
D10
D11
D9
D8
D6
D7
D5
D4
D3
RESULT 1
ACQUISITION CONVERSION
ACQUISITION
CONVERSION
HIGH-Z
Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
A/D STATE
IDLE
9
24
25
32
16
17
START
SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
D11 D10 D9
D7
D8
D6
D5
D4
D2
D3
D1 D0
START SEL2 SEL1 SEL0
BIP
RNG
PD1 PD0
CONTROL BYTE
RESULT
CONTROL BYTE 1
CB 2
16 SCLK
SSTRB
D10
D11
D9
D8
D6
D7
D5
D4
D3
RESULT 1
ACQUISITION CONVERSION
HIGH-Z
1
8
Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing
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