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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX1264AEEG+T |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT 400KSPS 24-QSOP |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 2,500 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 400k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 骞惰伅(li谩n) |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 9.5mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-SSOP锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 24-QSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 4 鍊嬪柈绔紝鍠サ锛�4 鍊嬪柈绔紝闆欐サ锛�2 鍊嬪伣宸垎锛屽柈妤�锛�2 鍊嬪伣宸垎锛岄洐妤� |
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Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within (GND - 300mV) to (VDD + 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD + 50mV) or be
less than (GND - 50mV).
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
Track/Hold
The MAX1262/MAX1264 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part enters
its hold mode on the fourth falling edge of clock after
writing the control byte. Note that, in internal clock mode,
this is approximately 1s after writing the control byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive (+) input. In
pseudo-differential operation, IN- connects to the nega-
tive (-) input and the difference of |(IN+) - (IN-)| is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal鈥檚 source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
tACQ = 9(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (800
) is the input resistance, and CIN (12pF) is
the input capacitance of the ADC. Source impedances
below 3k
have no significant impact on the MAX1262/
MAX1264s鈥� AC performance.
Higher source impedances can be used if a 0.01F
capacitor is connected to the individual analog inputs.
Along with the input impedance, this capacitor forms
an RC filter, limiting the ADC鈥檚 signal bandwidth.
Input Bandwidth
The MAX1262/MAX1264 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth that make it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC鈥檚
sampling rate by using undersampling techniques. To
avoid aliasing high-frequency signals into the frequen-
cy band of interest, anti-alias filtering is recommended.
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1262/MAX1264 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
MAX1262/MAX1264
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
10
______________________________________________________________________________________
CH0
CH2
CH1
CH3
CH4
CH6
CH7
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR
鈥�
+
12pF
SINGLE-ENDED MODE: IN+ = CH0鈥揅H7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3a. MAX1262 Simplified Input Structure
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800
CHOLD
HOLD
12-BIT CAPACITIVE DAC
REF
ZERO
COMPARATOR
鈥�
+
12pF
SINGLE-ENDED MODE: IN+ = CH0鈥揅H3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 3b. MAX1264 Simplified Input Structure
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| VE-254-MX-F4 | CONVERTER MOD DC/DC 48V 75W |
| MS3126E10-6P | CONN PLUG 6POS STRAIGHT W/PINS |
| V300A28T500BG2 | CONVERTER MOD DC/DC 28V 500W |
| VE-254-MX-F3 | CONVERTER MOD DC/DC 48V 75W |
| MS27474T24B61PA | CONN RCPT 61POS JAM NUT W/PINS |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX1264BCEG | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX1264BCEG+ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 4Ch 400ksps 5.5V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX1264BCEG+T | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12-Bit 4Ch 400ksps 5.5V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX1264BCEG-T | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX1264BEEG | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
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