with Internal Temperature Sensor and VDD
參數(shù)資料
型號: MAX1254BEUE+
廠商: Maxim Integrated Products
文件頁數(shù): 14/29頁
文件大?。?/td> 0K
描述: IC ADC 12BIT W/REF 16-TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 96
位數(shù): 12
采樣率(每秒): 94k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個單端,單極;8 個單端,雙極;4 個差分,單極;4 個差分,雙極
產(chǎn)品目錄頁面: 1396 (CN2011-ZH PDF)
MAX1253/MAX1254
Stand-Alone, 10-Channel, 12-Bit System Monitors
with Internal Temperature Sensor and VDD Monitor
______________________________________________________________________________________
21
Channel Configuration Register
Each channel has a channel configuration register
(Table 13) defining the number of consecutive faults to
be detected before setting the alarm bits and generat-
ing an interrupt, as well as controlling the digital averag-
ing. At power-up and after a RESET command, the
register defaults to 00 hex (no averaging, alarm on first
fault).
Fault Bits
The value stored in the fault bits (B7–B4) in the channel
configuration register sets the number of faults that
must occur for that channel before generating an inter-
rupt. Encoding of the fault bits is straight binary with
valves 0 to 15. A fault occurs in a channel when the
value in its current data register is outside the range
defined by the channel’s upper and lower threshold
registers. For example, if the number of faults set by the
fault bits is N, an interrupt is generated when the num-
ber of consecutive faults (see note below) reach (N +
1). The fault bits default to 0 hex at power-up.
Note: Consecutive faults are those happening in con-
secutive conversion scans for the same channel. If a
fault occurs and the next scan finds the input within the
normal range defined by the thresholds, the fault
counter resets. If the next counter finds the input signal
outside the opposite threshold, rather than the previous
one, the fault counter also resets. The fault counter
increments only when counting consecutive faults
exceeding the same threshold (Figure 4).
Averaging
The averaging calculated by the data-acquisition algo-
rithm of the MAX1253/MAX1254 improves the input sig-
nal-to-noise ratio (SNR) by reducing the signal
bandwidth digitally. The formula below describes the
filter implemented in the MAX1253/MAX1254:
current value = [(N - 1) / N] x past value +
[(present value) / N]
where N = number of samples indicated in Table 14.
The averaging bits (B3–B0) in the channel configuration
register can set the N factor to any value in Table 14.
The output of the filter-running algorithm is continuously
available in the current data register. The starting value
used by the algorithm is the initial state of the current
data register. The current data register is reset to mid-
scale (800 hex) at power-up or after a RESET com-
mand, but it can be loaded with a more appropriate
initial value to improve the filter settling time.
At power-up or after a RESET command, the B3–B0
bits of the channel configuration register are set to 0
hex, corresponding to a number of averaged N = 1, no
averaging. See Table 13 and the Write-Selected
Channel Configuration Registers section for program-
ming details. See Table 14 for N encoding.
As in all digital filters, truncation can be a cause of sig-
nificant errors. In the MAX1253/MAX1254, 24 bits of
precision are maintained in the digital averaging func-
tion, maintaining a worst-case truncation error of well
below an LSB. The worst-case truncation error in the
MAX1253/MAX1254 is given by the following:
where N = number of conversions averaged.
Therefore, the worst truncation error when averaging
256 samples is 0.0623 LSBs.
worst case truncation error
N
LSBs
-
=
1
4096
Table 13. Channel Configuration Register Format
B7 (MSB)
B6
B5
B4
B3
B2
B1
B0 (LSB)
Fault B3
Fault B2
Fault B1
Fault B0
Ave B3
Ave B2
Ave B1
Ave B0
Table 14. Conversion Average Encoding
CODE
N
0000
1, no averaging
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
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