參數(shù)資料
型號： MAX1249BEEE+T
廠商： Maxim Integrated Products
文件頁數(shù)： 20/24頁
文件大小： 0K
描述： IC ADC 10BIT SERIAL 16-QSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
采樣率（每秒）： 133k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 667mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1248—internal reference, offset nulled; MAX1249 — external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7 Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300Vp-p.
Note 10 Guaranteed by design. Not subject to production testing.
Note 11: The MAX1249 typically draws 400
A less than the values shown.
Note 12: Measured as
|V
FS(2.7V) - VFS(5.25V)|.
DIN to SCLK Setup
ns
240
tSTR
CS Rise to SSTRB Output Disable
ns
240
tSDV
CS Fall to SSTRB Output Enable
240
tSSTRB
SCLK Fall to SSTRB
ns
200
tCL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS to SCLK Rise Hold
ns
100
tCSS
CS to SCLK Rise Setup
ns
240
tTR
CS Rise to Output Disable
ns
240
tDV
CS Fall to Output Enable
tDO
SCLK Fall to Output Data Valid
ns
0
tDH
DIN to SCLK Hold
ns
s
1.5
tACQ
Acquisition Time
0
tSCK
SSTRB Rise to SCLK Rise
ns
100
tDS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internal clock mode only (Note 10)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS
ns
20
240
Figure 1
tCSH
tCH
ns
MAX124_ _C/E
MAX124_ _M
20
200
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