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參數資料
| 型號： | MAX1243BMJA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V to %.25V, Low-Power, 10-Bit Serial ADCs in SO-8 |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 158K |
| 代理商： | MAX1243BMJA |
M
+2.7V to +5.25V, Low-Power, 10-Bit
S erial ADCs in S O-8
10
______________________________________________________________________________________
External Cloc k
The actual conversion does not require the external
clock. This allows the conversion result to be read back
at the μP’s convenience at any clock rate up to
2.1MHz. The clock duty cycle is unrestricted if each
clock phase is at least 200ns. Do not run the clock
while a conversion is in progress.
T iming and Control
Conversion-start and data-read operations are con-
trolled by the
CS
and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline serial-interface
operation.
A
CS
falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK must be kept low during the conver-
sion. An internal register stores the data when the con-
version is in progress.
EOC is signaled by DOUT going high. DOUT’s rising
edge can be used as a framing signal. SCLK shifts the
data out of this register any time after the conversion is
complete. DOUT transitions on SCLK’s falling edge.
The next falling clock edge produces the MSB of the
conversion at DOUT, followed by the remaining bits.
Since there are 10 data bits, two sub-bits, and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur-
ring after the conversion result has been clocked out,
and prior to a rising edge of
CS
, produce trailing zeros
at DOUT and have no effect on converter operation.
For minimum cycle time, use DOUT’s rising edge as
the EOC signal and then clock out the data with 10.5
clock cycles at full speed (Figure 8b). Pull
CS
high after
reading the conversion’s LSB. After the specified mini-
mum time, t
CS
, pull
CS
low again to initiate the next
conversion.
Output Coding and T ransfer Func tion
The data output from the MAX1242/MAX1243 is binary.
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive-integer
LSB values. If V
REF
= 2.5V, then 1LSB = 2.44mV or
2.5V / 1024.
__________Applic ations Information
Connec tion to S tandard Interfac es
The MAX1242/MAX1243 serial interface is fully compat-
ible with SPI, QSPI, and Microwire standard serial inter-
faces (Figure 11).
CS
SCLK
DOUT
I/O
SCK
MISO
+3V
SS
a) SPI
CS
SCLK
DOUT
CS
SCK
MISO
+3V
SS
b) QSPI
MAX1242
MAX1243
MAX1242
MAX1243
MAX1242
MAX1243
CS
SCLK
DOUT
I/O
SK
SI
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1242/MAX1243
Figure 10. Unipolar Transfer Function, Full Scale (FS) =
V
REF
- 1LSB, Zero Scale (ZS) = GND
11
…
111
11
…
110
11
…
101
00
…
011
00
…
010
00
…
001
00
…
000
0
1
2
INPUT VOLTAGE (LSB)
FS
OUTPUT CODE
FS - 3/2LSB
FS = V
REF
- 1LSB
1LSB = V
REF
1024
FULL-SCALE
TRANSITION
3
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