參數(shù)資料
型號: MAX1242BCSA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 3-to-1 DVI/HDMI Switch with AC coupling 80-TQFP 0 to 70
中文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 4/12頁
文件大?。?/td> 158K
代理商: MAX1242BCSA
M
+2.7V to +5.25V, Low-Power, 10-Bit
S erial ADCs in S O-8
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, circuit of Figure 9, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Tested at V
DD
= +2.7V.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:
Offset nulled.
Note 4:
Sample tested to 0.1% AQL.
Note 5:
External load should not change during conversion for specified accuracy.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Measured as [V
FS
(V
DD(min)
) - V
FS
(V
DD(max)
)].
Note 8:
To guarantee acquisition time, t
ACQ
is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
DOUT
DOUT
6k
DGND
C
LOAD
= 50pF
C
LOAD
= 50pF
6k
DGND
+2.7V
b)
High-Z to V
OL
and V
OH
to V
OL
a)
High-Z to V
OH
and V
OL
to V
OH
DOUT
DOUT
6k
DGND
C
LOAD
= 50pF
C
LOAD
= 50pF
6k
DGND
+2.7V
b)
V
OL
to High-Z
a)
V
OH
to High-Z
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX124_ _M
MAX124_ _C/E
Figure 1, C
LOAD
= 50pF
Figure 2, C
LOAD
= 50pF
Figure 1,
C
LOAD
= 50pF
CS
= V
DD
(Note 8)
CONDITIONS
ns
ns
MHz
ns
ns
240
240
2.1
t
DV
t
TR
f
SCLK
t
CH
t
CL
CS
Fall to Output Enable
CS
Rise to Output Disable
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
ns
20
20
200
240
t
DO
μs
1.5
t
ACQ
Acquisition Time
SCLK Fall to Output Data Valid
ns
240
t
CS
CS
Pulse Width
ns
0
t
STR
DOUT Rise to SCLK Rise (Note 6)
ns
50
t
CS0
SCLK Low to
CS
Fall Setup Time
0
200
200
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
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