參數(shù)資料
型號: MAX1231BEEG-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference
中文描述: 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封裝: QSOP-24
文件頁數(shù): 5/24頁
文件大?。?/td> 512K
代理商: MAX1231BEEG-T
M
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
208
100
40
TYP
MAX
UNITS
Externally clocked conversion
Data I/O
SCLK Clock Period
t
CP
ns
SCLK Duty Cycle
SCLK Fall to DOUT Transition
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS
to SCLK Rise Setup
SCLK Rise to
CS
Hold
t
CH
t
DOT
t
DOD
t
DOE
t
DS
t
DH
t
CSS
t
CSH
t
CSW
60
40
40
40
40
%
ns
ns
ns
ns
ns
ns
ns
ns
μs
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
0
40
0
40
1.4
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
Temp sense
Voltage conversion
Reference power-up
CNVST
Pulse Width
t
T S
55
7
65
CS
or
CNVST
Rise to
EOC
Low (Note 9)
μs
TIMING CHARACTERISTICS (Figure 1)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0
1024
2048
3072
4096
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
M
OUTPUT CODE
I
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0
1024
2048
3072
4096
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
M
OUTPUT CODE
D
SINAD vs. FREQUENCY
M
FREQUENCY (kHz)
A
100
10
1
10
20
40
30
60
50
90
80
70
100
0
0.1
1000
Typical Operating Characteristics
(V
DD
= +3V, V
REF
= +2.5V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25
°
C, unless otherwise noted.)
Note 9:
This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive. The internal reference is always used for temperature measure-
ments.
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