參數(shù)資料
型號: MAX1224CTC+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/18頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 1.5MSPS 12-TQFN
標準包裝: 2,500
位數(shù): 12
采樣率(每秒): 1.5M
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 18mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 12-WQFN 裸露焊盤
供應商設備封裝: 12-TQFN-EP(4x4)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,單極
MAX1224/MAX1225
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
High-frequency noise in the VDD power supply can
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01F
and 10F bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1224/MAX1225 are mea-
sured using the end-points method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
16
______________________________________________________________________________________
MAX1224
MAX1225
ADSP21_ _ _
VL
SCLK
CNVST
DOUT
VDDINT
RCLK
RFS
TCLK
TFS
DR
Figure 19. Interfacing to the ADSP21_ _ _
10
μF
0.1
μF
10
μF
0.1
μF
GND
VL
SUPPLIES
DGND
VL
DIGITAL
CIRCUITRY
VDD
GND RGND
VL
MAX1224
MAX1225
Figure 20. Power-Supply Grounding Condition
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
DOUT
SCLK
CNVST
0
1
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
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