參數(shù)資料
型號(hào)： MAX1207
廠商： Maxim Integrated Products, Inc.
英文描述： 40Msps, 12-Bit ADC
中文描述： 12位，65Msps ADC
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 609K
代理商： MAX1207
M
40Msps, 12-Bit ADC
______________________________________________________________________________________
15
-0.28
-0.26
-0.24
-0.22
-0.20
-0.18
-0.16
-0.14
-0.12
-40
-15
10
35
60
85
OFFSET ERROR
vs. TEMPERATURE
M
TEMPERATURE (
°
C)
O
V
REFIN
= 2.048V
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-40
10
-15
35
60
85
GAIN ERROR
vs. TEMPERATURE
M
TEMPERATURE (
°
C)
G
V
REFIN
= 2.048V
Pin Description
PIN
NAME
FUNCTION
1
REFP
Positive Reference I/O. Conversion range is
±
(V
REFP
- V
REFN
). Bypass REFP to GND with a 0.1μF
capacitor. Connect a 1μF capacitor in parallel with a 10μF capacitor between REFP and REFN.
2
REFN
Negative Reference I/O. Conversion range is
±
(V
REFP
- V
REFN
). Bypass REFN to GND with a 0.1μF
capacitor. Connect a 1μF capacitor in parallel with a 10μF capacitor between REFP and REFN.
3
COM
Common-Mode Voltage I/O. Bypass COM to GND with a
≥
2.2μF capacitor in parallel with a 0.1μF
capacitor.
4, 7, 16, 35
GND
Ground. Connect all ground pins and the EP together.
5
INP
Positive Analog Input. For single-ended input operation, connect signal source to INP and connect INN
to COM. For differential operation, connect the input signal between INP and INN.
6
INN
Negative Analog Input. For single-ended input operation, connect INN to COM. For differential operation,
connect the input signal between INP and INN.
8
DCE
Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OV
DD
or DV
DD
) to enable the internal duty-cycle equalizer.
9
CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OV
DD
or V
DD
), connect the clock
signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the clock signal
to CLKP and tie CLKN to GND.
10
CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OV
DD
or V
DD
), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.
Typical Operating Characteristics (continued)
(V
DD
= 3.3V, OV
DD
= 2.0V, GND = 0, REFIN = REFOUT (internal reference), C
REFOUT
= 0.1μF, C
L
≈
5pF at digital outputs, V
IN
= -0.5dBFS
differential input, DCE = high, CLKTYP = high, PD = low, G/
T
= low, f
CLK
= 40MHz (50% duty cycle), C
REFP
= C
REFN
= 0.1μF to GND, 1μF
in parallel with 10μF between REFP and REFN, C
COM
= 0.1μF in parallel with 2.2μF to GND, T
A
= +25
°
C, unless otherwise noted.)
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