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參數資料
| 型號： | MAX1204BEAP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 20/23頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 8CH 20-SSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數： | 10 |
| 采樣率（每秒）： | 133k |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 640mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
CLOAD = 100pF
MAX1204
5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
6
Maxim Integrated
External clock mode only, CLOAD = 100pF
ns
240
CLOAD = 100pF
ns
20
240
tDO
SCLK Fall to Output Data Valid
CONDITIONS
240
tDV
CS Fall to Output Enable
CLOAD = 100pF
ns
240
tTR
CS Rise to Output Disable
tSDV
CS Fall to SSTRB Output Enable
(Note 6)
External clock mode only, CLOAD = 100pF
ns
240
tSTR
CS Rise to SSTRB Output
Disable (Note 6)
Internal clock mode only
ns
0
tSCK
SSTRB Rise to SCLK Rise
(Note 6)
ns
0
tDH
DIN to SCLK Hold
s
1.5
tACQ
Acquisition Time
ns
100
tDS
DIN to SCLK Setup
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = 2.7V to 3.6V, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.)
ns
100
tCSS
CS to SCLK Rise Setup
ns
0
tCSH
CS to SCLK Rise Hold
ns
200
tCH
SCLK Pulse Width High
ns
200
tCL
SCLK Pulse Width Low
CLOAD = 100pF
ns
240
tSSTRB
SCLK Fall to SSTRB
CLOAD = 100pF
Note 1:
Tested at VDD = 5.0V; VSS = 0V; unipolar input mode.
Note 2:
Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3:
Internal reference, offset nulled.
Note 4:
On-channel grounded; sine-wave applied to all off-channels.
Note 5:
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
Guaranteed by design. Not subject to production testing.
Note 7:
Common-mode range for analog inputs is from VSS to VDD.
Note 8:
External load should not change during the conversion for specified accuracy.
Note 9:
Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on fSCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at VSUPPLY +5% and VSUPPLY -5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
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