
M
5V, 8-Channel, S erial, 12-Bit ADCs
with 3V Digital Interfac e
18
______________________________________________________________________________________
Table 6. Software Shutdown
and Clock Mode
Table 5. Typical Power-Up Delay Times
Table 7. Hard-Wired Shutdown
and Compensation Mode
Figure 12a. Timing Diagram for Power-Down Modes, External Clock
POWERED UP
FULL
POWER-
DOWN
POWERED
UP
POWERED UP
DATA VALID
(12 DATA BITS)
DATA VALID
(12 DATA BITS)
DATA
INVALID
EXTERNAL
EXTERNAL
INTERNAL
S X X X X X 1 1
S
0 1
X
X
X
X
X
X X X X X
S
1 1
FAST
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS FAST
POWER-DOWN
MODE
133
2
Full
Disabled
133
2
Fast
Disabled
133
26
26
MAXIMUM
SAMPLING RATE
(ksps)
See Figure 14c
300
5
POWER-UP
DELAY
(μs)
Fast/Full
Full
Fast
POWER-DOWN
MODE
4.7
REF
CAPACITOR
(μF)
External
Enabled
REFERENCE
BUFFER
Internal
Enabled
Internal
Enabled
REFERENCE-BUFFER
COMPENSATION MODE
N/A
Full
Power-Down
GND
SHDN
STATE
External compensation
Enabled
Floating
Internal compensation
Enabled
V
DD
REFERENCE-BUFFER
COMPENSATION
DEVICE
MODE
External clock mode
1
1
Internal clock mode
0
1
PD1
Fast power-down mode
1
0
Full power-down mode
0
0
DEVICE MODE
PD0