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參數(shù)資料
| 型號： | MAX1198EVKIT |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR MAX1198 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 100M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 輸入范圍： | ±1 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 264mW @ 100MSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | MAX1195，1196，1197，1198 |
| 已供物品： | 板 |
Detailed Description
The MAX1198 uses a seven-stage, fully differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been processed
by all seven stages.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
MAX1198
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________
11
Pin Description (continued)
PIN
NAME
FUNCTION
42
D5A
Three-State Digital Output, Bit 5, Channel A
43
D6A
Three-State Digital Output, Bit 6, Channel A
44
D7A
Three-State Digital Output, Bit 7 (MSB), Channel A
45
REFOUT
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-
divider.
46
REFIN
Reference Input. VREFIN = 2 x (VREFP - VREFN).
Bypass to GND with a >0.1F capacitor.
47
REFP
Positive Reference I/O. Conversion range is
±(VREFP - VREFN).
Bypass to GND with a >0.1F capacitor.
48
REFN
Negative Reference I/O. Conversion range is
±(VREFP - VREFN).
Bypass to GND with a >0.1F capacitor.
8
VINA
STAGE 1
STAGE 2
D7A–D0A
VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL ALIGNMENT LOGIC
STAGE 6
STAGE 7
2-BIT FLASH
ADC
T/H
8
VINB
STAGE 1
STAGE 2
D7B–D0B
DIGITAL ALIGNMENT LOGIC
STAGE 6
STAGE 7
2-BIT FLASH
ADC
T/H
Figure 1. Pipelined Architecture—Stage Blocks
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