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參數(shù)資料
| 型號： | MAX1198 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs |
| 中文描述： | 雙路、8位、100Msps、3.3V、低功耗ADC，內(nèi)置電壓基準及并行輸出 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大?。?/td> | 557K |
| 代理商： | MAX1198 |
M
The MAX1198 clock input operates with a voltage thresh-
old set to V
DD
/2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the
Electrical Characteristics
table
.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1198
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data (D0A/B–D7A/B), Output
Data Format Selection (T/B), Output
Enable (
OE
)
All digital outputs, D0A
–
D7A (channel A) and D0B
–
D7B
(channel B), are TTL/CMOS-logic compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output
coding can either be straight offset binary or two
’
s com-
plement (Table 1) controlled by a single pin (T/B). Pull
T/B low to select offset binary and high to activate two
’
s
complement output coding. The capacitive load on the
digital outputs D0A
–
D7A and D0B
–
D7B should be kept
as low as possible (<15pF), to avoid large digital cur-
rents that could feed back into the analog portion of the
MAX1198, thereby degrading its dynamic performance.
Using buffers on the digital outputs of the ADCs can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1198, small-series resistors (e.g., 100
) may
be added to the digital output paths close to the
MAX1198.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wakeup and data output valid.
Power-Down and Sleep Modes
The MAX1198 offers two power-save modes
—
sleep
mode (SLEEP) and full power-down (PD) mode. In
sleep mode (SLEEP = 1), only the reference bias circuit
is active (both ADCs are disabled), and current con-
sumption is reduced to 3.2mA.
To enter full power-down mode, pull PD high. With
OE
simultaneously low, all outputs are latched at the last
value prior to power-down. Pulling
OE
high forces the
digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended-to-differential converters. The internal
reference provides a V
DD
/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed op amps. The user can
select the R
ISO
and C
IN
values to optimize the filter per-
formance, to suit a particular application. For the appli-
cation in Figure 5, a R
ISO
of 50
is placed before the
capacitive load to prevent ringing and oscillation. The
22pF C
IN
capacitor acts as a small filter capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1198 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
DD
/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer can be selected to reduce the drive
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
14
______________________________________________________________________________________
OUTPUT
D7A
–
D0A
OE
t
DISABLE
t
ENABLE
HIGH-Z
HIGH-Z
VALID DATA
OUTPUT
D7B
–
D0B
HIGH-Z
HIGH-Z
VALID DATA
Figure 4. Output Timing Diagram
ST RA G HT
O F FSET
B NA R Y
T/B = 0
T WO
’
S
C O M PL EM EN T
D FF ER EN T AL
IN PU T
VO LT A G E*
D FF ER EN T AL
IN PU T
T/B = 1
V
REF
x 255/256
+Full Scale
- 1LSB
1111 1111
0111 1111
V
REF
x 1/256
0
-V
REF
x 1/256
+1LSB
Bipolar Zero
-1LSB
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
1111 1111
-V
REF
x 255/256
-Full Scale
+ 1LSB
0000 0001
1000 0001
-V
REF
x 256/256
-Full Scale
0000 0000
1000 0000
Table 1. MAX1198 Output Codes For
Differential Inputs
*
V
REF
= V
REFP
- V
REFN
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| MAX1198E/D | 功能描述:模數(shù)轉換器 - ADC DICE SALES DICE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| MAX1198ECM+TD | 功能描述:模數(shù)轉換器 - ADC 8-Bit 2Ch 100Msps 3.3V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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