- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2086 > MAX1196ECM+TD (Maxim Integrated Products)IC ADC 8BIT 40MSPS DL 48-TQFP PDF資料下載
參數(shù)資料
| 型號： | MAX1196ECM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 40MSPS DL 48-TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 108mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
12
______________________________________________________________________________________
Detailed Description
The MAX1196 uses a 7-stage, fully differential, pipelined
architecture (Figure 1) that allows for high-speed con-
version while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for CHA and 5.5 clock cycles
for CHB.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all 7 stages.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a, and S5b are closed. The fully differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a, S4b, S5a, and S5b are then
opened before switches S3a and S3b connect capaci-
tors C1a and C1b to the output of the amplifier and
switch S4c is closed. The resulting differential voltages
are held on capacitors C2a and C2b. The amplifiers are
used to charge capacitors C1a and C1b to the same
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1196
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1196 is determined by
the internally generated voltage difference between
REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4).
The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose.
8
VINA
STAGE 1
STAGE 2
DIGITAL ALIGNMENT LOGIC
STAGE 6
STAGE 7
2-BIT FLASH
ADC
T/H
8
VINB
STAGE 1
STAGE 2
DIGITAL ALIGNMENT LOGIC
STAGE 6
STAGE 7
2-BIT FLASH
ADC
T/H
OUTPUT MULTIPLEXER
8
D0A/B–D7A/B
Figure 1. Pipelined Architecture—Stage Blocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX1198ECM+TD | IC ADC 8BIT 100MSPS DL 48-TQFP |
| MAX1204AEPP+ | IC ADC 10BIT 8CH 20-DIP |
| MAX120ENG+ | IC ADC 12BIT 500KSPS 24-DIP |
| MAX1224CTC+T | IC ADC 12BIT 1.5MSPS 12-TQFN |
| MAX1230ACEG+T | IC ADC 12BIT 300KSPS 24-QSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1197ECM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX1197ECM+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 60Msps 3V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1197ECM+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 60Msps 3V High Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1197ECM-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1197ECM-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。